公开(公告)号：US08664766B2

公开(公告)日：2014-03-04

申请号：US12430436

申请日：2009-04-27

申请人： Chih-Chao Yang ,  Terry A. Spooner ,  Oscar van der Straten

发明人： Chih-Chao Yang ,  Terry A. Spooner ,  Oscar van der Straten

IPC分类号： H01L23/48

CPC分类号： H01L21/76831 ,  H01L21/02063 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/32131 ,  H01L21/76805 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76873 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure including a gouging feature at the bottom of one of the via openings. The structure includes an upper interconnect level including a second dielectric material having at least one conductively filled via and an overlying conductively filled line disposed therein. The conductively filled via is in contact with an exposed surface of the at least one conductive feature of a first interconnect level by an anchoring area. The conductively filled via is separated from the second dielectric material by a first diffusion barrier layer, and the conductively filled line is separated from the second dielectric material by a second continuous diffusion barrier layer thereby the second dielectric material includes no damaged regions in areas adjacent to the conductively filled line.

摘要翻译： 一种互连结构，包括在一个通孔开口的底部的气流特征。 该结构包括上部互连层，其包括具有至少一个导电填充通孔的第二电介质材料和布置在其中的上覆导电填充线。 导电填充的通孔通过锚固区域与第一互连水平的至少一个导电特征的暴露表面接触。 通过第一扩散阻挡层将导电填充的通孔与第二介电材料分离，并且通过第二连续扩散阻挡层将导电填充线与第二介电材料分离，由此第二介电材料在邻近的区域中不包括受损区域 导线填充线。

公开(公告)号：US08017522B2

公开(公告)日：2011-09-13

申请号：US11626550

申请日：2007-01-24

申请人： Qinghuang Lin ,  Terry A. Spooner ,  Darshan D. Gandhi ,  Christy S. Tyberg

发明人： Qinghuang Lin ,  Terry A. Spooner ,  Darshan D. Gandhi ,  Christy S. Tyberg

IPC分类号： H01L21/44 ,  H01L21/311

CPC分类号： H01L21/3105 ,  H01L21/76805 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76834

摘要： A mechanically robust semiconductor structure with improved adhesion strength between a low-k dielectric layer and a dielectric-containing substrate is provided. In particular, the present invention provides a structure that includes a dielectric-containing substrate having an upper region including a treated surface layer which is chemically and physically different from the substrate; and a low-k dielectric material located on a the treated surface layer of the substrate. The treated surface layer and the low-k dielectric material form an interface that has an adhesion strength that is greater than 60% of the cohesive strength of the weaker material on either side of the interface. The treated surface is formed by treating the surface of the substrate with at least one of actinic radiation, a plasma and e-beam radiation prior to forming of the substrate the low-k dielectric material.

摘要翻译： 提供了具有改善的低k电介质层和含电介质衬底之间的粘附强度的机械稳固的半导体结构。 特别地，本发明提供了一种结构，其包括含电介质的衬底，其具有包括化学和物理上不同于衬底的经处理的表面层的上部区域; 以及位于所述基板的经处理的表面层上的低k电介质材料。 经处理的表面层和低k电介质材料形成界面，该界面的粘合强度大于界面两侧的较弱材料的内聚强度的60％。 经处理的表面通过在形成低k电介质材料之前用光化辐射，等离子体和电子束辐射中的至少一种来处理衬底的表面而形成。

公开(公告)号：US20100314767A1

公开(公告)日：2010-12-16

申请号：US12485366

申请日：2009-06-16

申请人： Shyng-Tsong Chen ,  Qinghuang Lin ,  Sampath Purushothaman ,  Terry A. Spooner ,  Shawn M. Walsh

发明人： Shyng-Tsong Chen ,  Qinghuang Lin ,  Sampath Purushothaman ,  Terry A. Spooner ,  Shawn M. Walsh

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L23/5329 ,  H01L21/4846 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76831 ,  H01L23/49894 ,  H01L23/53295 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A self-aligned interconnect structure is provided that includes a first patterned and cured low-k material located on a surface of a substrate, wherein the first patterned and cured low-k material includes at least one first interconnect pattern (via or trench pattern) therein. A second patterned and cured low-k material having at least one second interconnect pattern that is different from the first interconnect pattern is located atop the first patterned and cured low k material. A portion of the second patterned and cured low-k material partially fills the at least one first interconnect within the first patterned and cured low-k material. A conductive material fills the at least one first interconnect pattern and the at least one second interconnect pattern. A method of forming such a self-aligned interconnect structure is also provided.

摘要翻译： 提供了自对准的互连结构，其包括位于衬底的表面上的第一图案化和固化的低k材料，其中第一图案化和固化的低k材料包括至少一个第一互连图案（通孔或沟槽图案） 其中。 具有不同于第一互连图案的至少一个第二互连图案的第二图案化和固化的低k材料位于第一图案化和固化的低k材料的顶部。 第二图案化和固化的低k材料的一部分部分地填充第一图案化和固化的低k材料内的至少一个第一互连。 导电材料填充至少一个第一互连图案和至少一个第二互连图案。 还提供了形成这种自对准互连结构的方法。

公开(公告)号：US20090072401A1

公开(公告)日：2009-03-19

申请号：US11857805

申请日：2007-09-19

申请人： John C. Arnold ,  Sampath Purushothaman ,  Muthumanickam Sankarapandian ,  Hosadurga K. Shobha ,  Terry A. Spooner

发明人： John C. Arnold ,  Sampath Purushothaman ,  Muthumanickam Sankarapandian ,  Hosadurga K. Shobha ,  Terry A. Spooner

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L23/5329 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L2924/0002 ,  H01L2924/00

摘要： Plasma damage in ultra low k dielectric materials during formation of a dual damascene metal interconnect structure is reduced by providing a protective spacer on sidewalls of a line trench. A densified trench bottom region may be additionally formed directly beneath an exposed horizontal surface of the line trench. The protective spacer and/or the densified trench bottom region protects an ultra low k intermetal dielectric layer from plasma damage during a plasma strip process that is used to remove a disposable via fill plug employed in the dual damascene metal interconnect structure.

摘要翻译： 在形成双镶嵌金属互连结构的超低k电介质材料中的等离子体损伤通过在管线沟槽的侧壁上设置保护隔离物来减少。 致密沟槽底部区域可以直接附加地形成在线沟槽的暴露的水平表面下方。 保护间隔物和/或致密的沟槽底部区域在用于去除在双镶嵌金属互连结构中使用的一次性通孔填充塞的等离子体条带过程中保护超低k金属间介电层免受等离子体损伤。

公开(公告)号：US20090026625A1

公开(公告)日：2009-01-29

申请号：US12245133

申请日：2008-10-03

申请人： Chih-Chao Yang ,  Griselda Bonilla ,  Qinghuang Lin ,  Terry A. Spooner

发明人： Chih-Chao Yang ,  Griselda Bonilla ,  Qinghuang Lin ,  Terry A. Spooner

IPC分类号： H01L23/52

CPC分类号： H01L23/53295 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76844 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure and method of fabricating the same in which the adhesion between a chemically etched dielectric material and a noble metal liner is improved are provided. In accordance with the present invention, a chemically etching dielectric material is subjected to a treatment step which modified the chemical nature of the dielectric material such that the treated surfaces become hydrophobic. The treatment step is performed prior to deposition of the noble metal liner and aides in improving the adhesion between the chemically etched dielectric material and the noble metal liner.

摘要翻译： 提供了一种互连结构及其制造方法，其中改善了化学蚀刻的电介质材料和贵金属衬垫之间的粘合性。 根据本发明，对化学蚀刻电介质材料进行改性电介质材料的化学性质使得被处理的表面变得疏水的处理步骤。 在沉积贵金属衬垫和助剂以改善化学蚀刻的电介质材料和贵金属衬垫之间的粘附性之前进行处理步骤。

公开(公告)号：US20080173984A1

公开(公告)日：2008-07-24

申请号：US11626550

申请日：2007-01-24

申请人： Qinghuang Lin ,  Terry A. Spooner ,  Darshan D. Gandhi ,  Christy S. Tyberg

发明人： Qinghuang Lin ,  Terry A. Spooner ,  Darshan D. Gandhi ,  Christy S. Tyberg

IPC分类号： H01L23/58 ,  H01L21/31

CPC分类号： H01L21/3105 ,  H01L21/76805 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76834

摘要： A mechanically robust semiconductor structure with improved adhesion strength between a low-k dielectric layer and a dielectric-containing substrate is provided. In particular, the present invention provides a structure that includes a dielectric-containing substrate having an upper region including a treated surface layer which is chemically and physically different from the substrate; and a low-k dielectric material located on a the treated surface layer of the substrate. The treated surface layer and the low-k dielectric material form an interface that has an adhesion strength that is greater than 60% of the cohesive strength of the weaker material on either side of the interface. The treated surface is formed by treating the surface of the substrate with at least one of actinic radiation, a plasma and e-beam radiation prior to forming of the substrate the low-k dielectric material.

摘要翻译： 提供了具有改善的低k电介质层和含电介质衬底之间的粘附强度的机械稳固的半导体结构。 特别地，本发明提供了一种结构，其包括含电介质的衬底，其具有包括化学和物理上不同于衬底的经处理的表面层的上部区域; 以及位于所述基板的经处理的表面层上的低k电介质材料。 经处理的表面层和低k电介质材料形成界面，该界面的粘合强度大于界面两侧的较弱材料的内聚强度的60％。 经处理的表面通过在形成低k电介质材料之前用光化辐射，等离子体和电子束辐射中的至少一种来处理衬底的表面而形成。

公开(公告)号：US20120329269A1

公开(公告)日：2012-12-27

申请号：US13602119

申请日：2012-09-01

申请人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

发明人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

IPC分类号： H01L21/768

CPC分类号： H01L21/76808 ,  H01L21/02063 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02348 ,  H01L21/02362 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/31633 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831

摘要： Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.

摘要翻译： 提供了最小化或消除对低k和超低k有机硅酸盐金属间电介质层的等离子体损伤的方法。 等离子体损伤的降低通过在合适的点处中断蚀刻和剥离工艺流程来实现，以增加本发明的处理，其保护金属间电介质层免受等离子体条带处理期间的等离子体损伤。 以这种方式减少或消除等离子体损伤区域还能够减少光致抗蚀剂中的线图案和由其形成的金属线之间的线偏压，并且由于在反应性之后的湿清洁而改变线沟槽的线宽 用于形成线沟槽和通孔腔的离子蚀刻。 减少的线偏压对金属互连结构的电产量具有有益的影响。

公开(公告)号：US07795740B2

公开(公告)日：2010-09-14

申请号：US12245133

申请日：2008-10-03

申请人： Chih-Chao Yang ,  Griselda Bonilla ,  Qinghuang Lin ,  Terry A. Spooner

发明人： Chih-Chao Yang ,  Griselda Bonilla ,  Qinghuang Lin ,  Terry A. Spooner

IPC分类号： H01L21/4763 ,  H01L23/48

CPC分类号： H01L23/53295 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76844 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure and method of fabricating the same in which the adhesion between a chemically etched dielectric material and a noble metal liner is improved are provided. In accordance with the present invention, a chemically etching dielectric material is subjected to a treatment step which modified the chemical nature of the dielectric material such that the treated surfaces become hydrophobic. The treatment step is performed prior to deposition of the noble metal liner and aides in improving the adhesion between the chemically etched dielectric material and the noble metal liner.

摘要翻译： 提供了一种互连结构及其制造方法，其中改善了化学蚀刻的电介质材料和贵金属衬垫之间的粘合性。 根据本发明，对化学蚀刻电介质材料进行改性电介质材料的化学性质使处理后的表面变得疏水的处理步骤。 在沉积贵金属衬垫和助剂以改善化学蚀刻的电介质材料和贵金属衬垫之间的粘附性之前进行处理步骤。

公开(公告)号：US07781332B2

公开(公告)日：2010-08-24

申请号：US11857805

申请日：2007-09-19

申请人： John C. Arnold ,  Sampath Purushothaman ,  Muthumanickam Sankarapandian ,  Hosadurga K. Shobha ,  Terry A. Spooner

发明人： John C. Arnold ,  Sampath Purushothaman ,  Muthumanickam Sankarapandian ,  Hosadurga K. Shobha ,  Terry A. Spooner

IPC分类号： H01L21/4763 ,  H01L21/302

CPC分类号： H01L23/5329 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L2924/0002 ,  H01L2924/00

摘要： Plasma damage in ultra low k dielectric materials during formation of a dual damascene metal interconnect structure is reduced by providing a protective spacer on sidewalls of a line trench. A densified trench bottom region may be additionally formed directly beneath an exposed horizontal surface of the line trench. The protective spacer and/or the densified trench bottom region protects an ultra low k intermetal dielectric layer from plasma damage during a plasma strip process that is used to remove a disposable via fill plug employed in the dual damascene metal interconnect structure.

摘要翻译： 在形成双镶嵌金属互连结构的超低k电介质材料中的等离子体损伤通过在管线沟槽的侧壁上设置保护隔离物来减少。 致密沟槽底部区域可以直接附加地形成在线沟槽的暴露的水平表面下方。 保护间隔物和/或致密的沟槽底部区域在用于去除在双镶嵌金属互连结构中使用的一次性通孔填充塞的等离子体条带过程中保护超低k金属间介电层免受等离子体损伤。

公开(公告)号：US20070273044A1

公开(公告)日：2007-11-29

申请号：US11440984

申请日：2006-05-25

申请人： Chih-Chao Yang ,  Griselda Bonilla ,  Qinghuang Lin ,  Terry A. Spooner

发明人： Chih-Chao Yang ,  Griselda Bonilla ,  Qinghuang Lin ,  Terry A. Spooner

IPC分类号： H01L23/52

CPC分类号： H01L23/53295 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76844 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure and method of fabricating the same in which the adhesion between a chemically etched dielectric material and a noble metal liner is improved are provided. In accordance with the present invention, a chemically etching dielectric material is subjected to a treatment step which modified the chemical nature of the dielectric material such that the treated surfaces become hydrophobic. The treatment step is performed prior to deposition of the noble metal liner and aides in improving the adhesion between the chemically etched dielectric material and the noble metal liner.

摘要翻译： 提供了一种互连结构及其制造方法，其中改善了化学蚀刻的电介质材料和贵金属衬垫之间的粘合性。 根据本发明，对化学蚀刻电介质材料进行改性电介质材料的化学性质使处理后的表面变得疏水的处理步骤。 在沉积贵金属衬垫和助剂以改善化学蚀刻的电介质材料和贵金属衬垫之间的粘附性之前进行处理步骤。