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    Semiconductor storage apparatus
    21.
    发明申请
    Semiconductor storage apparatus 有权
    半导体存储装置

    公开(公告)号：US20070061507A1

    公开(公告)日：2007-03-15

    申请号：US11519221

    申请日：2006-09-12

    申请人： Shunichi Iwanari ,  Yasushi Gohou ,  Yoshihisa Kato

    发明人： Shunichi Iwanari ,  Yasushi Gohou ,  Yoshihisa Kato

    IPC分类号： G06F13/00 ,  G06F12/08 ,  G06F12/00

    CPC分类号： G06F12/123 ,  G06F2212/2022

    摘要： A semiconductor storage apparatus comprising: a ferroelectric memory; an SRAM 30; a counter 41; a CAM 10 that judges whether or not a block of data requested to be read out from the ferroelectric memory is stored in the SRAM 30; a storage control unit 51 that, if a result of the judgment is negative, performs a control to read out the requested block of data from the ferroelectric memory and stores a copy of the read-out block of data into a unit storage area in the SRAM 30 that corresponds to the count value indicated by the counter 41; and a counter control unit 52 that causes the counter 41 to update the count value each time a result of the judgment is negative.

    摘要翻译： 一种半导体存储装置，包括：铁电存储器; 一个SRAM 30; 柜台41 判断从铁电存储器请求读出的数据块是否存储在SRAM30中的CAM10; 存储控制单元51，如果判断结果为否定，则执行控制以从强电介质存储器读出所请求的数据块，并将读出的数据块的副本存储在该单元存储区域中 对应于由计数器41指示的计数值的SRAM 30; 以及计数器控制单元52，每当判断结果为负时，使计数器41更新计数值。

    Semiconductor memory device
    23.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5841727A

    公开(公告)日：1998-11-24

    申请号：US867855

    申请日：1997-06-03

    申请人： Shunichi Iwanari ,  Hirohito Kikukawa

    发明人： Shunichi Iwanari ,  Hirohito Kikukawa

    IPC分类号： G11C11/408 ,  G11C8/12 ,  G11C11/401 ,  G11C11/406 ,  G11C8/00

    CPC分类号： G11C8/12 ,  G11C11/406

    摘要： To restrain an increase in power consumption and a reduction in access speed, the following structure is adopted: An address is input to a row address input circuit and in correspondence with a row address output from the row address input circuit, a predecode signal is output from a row predecode circuit. An address is input to a block-select-signal generating circuit from which first and second block select signals are output for selecting either one of the first and second memory cell array blocks. First and second predecode-signal hold circuits provided in correspondence with the first and second memory cell array blocks hold predecode signals. First and second predecode signals held by the first and second predecode signal hold circuits are supplied to first and second row decode circuits, respectively, and the first and second predecode-signal hold circuits corresponding to the first and second block select signals update the contents being held.

    摘要翻译： 为了抑制功耗的增加和存取速度的降低，采用以下结构：将地址输入到行地址输入电路，并且与从行地址输入电路输出的行地址对应地输出预解码信号 来自一行预先解码电路。 地址被输入到块选择信号发生电路，从其输出第一和第二块选择信号以选择第一和第二存储单元阵列块中的任一个。 与第一和第二存储单元阵列块对应地设置的第一和第二预解码信号保持电路保持预解码信号。 由第一和第二预解码信号保持电路保持的第一和第二预解码信号分别被提供给第一和第二行解码电路，并且对应于第一和第二块选择信号的第一和第二预解码信号保持电路更新内容为 保持。

    Semiconductor integrated circuit with a data transmission circuit
    25.
    发明授权
    Semiconductor integrated circuit with a data transmission circuit 失效
    具有数据传输电路的半导体集成电路

    公开(公告)号：US5642323A

    公开(公告)日：1997-06-24

    申请号：US573076

    申请日：1995-12-15

    申请人： Hisakazu Kotani ,  Hironori Akamatsu ,  Ichiro Nakao ,  Toshio Yamada ,  Akihiro Sawada ,  Hirohito Kikukawa ,  Masashi Agata ,  Shunichi Iwanari

    发明人： Hisakazu Kotani ,  Hironori Akamatsu ,  Ichiro Nakao ,  Toshio Yamada ,  Akihiro Sawada ,  Hirohito Kikukawa ,  Masashi Agata ,  Shunichi Iwanari

    IPC分类号： G11C5/02 ,  G11C7/10 ,  G11C11/4096 ,  G11C7/00

    CPC分类号： G11C7/1057 ,  G11C11/4096 ,  G11C5/025 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069

    摘要： In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

    摘要翻译： 在用于驱动一对数据线的驱动电路中，差分输入信号的幅度从2.5V减小到小于常规下限电源电压（约1.5V）的0.6V。 通过一对数据线传输的差分信号的幅度被放大电路放大到2.5V，然后由锁存电路锁存所得到的信号。 在锁存电路锁存之后，停止放大电路的工作。 驱动电路仅由多个NMOS晶体管构成，以便不增加在断开状态下流动的漏电流。 这里，位于地侧的NMOS晶体管的阈值电压降低到常规的下限值（0.3V〜0.6V），而电源侧的NMOS晶体管的阈值电压低于 上述下限值（0V至0.3V），从而增强了在电源侧的NMOS晶体管的驱动力。

    Semiconductor memory device having a prolonged data holding time
    26.
    发明授权
    Semiconductor memory device having a prolonged data holding time 失效
    半导体存储器件具有延长的数据保持时间

    公开(公告)号：US5426601A

    公开(公告)日：1995-06-20

    申请号：US184933

    申请日：1994-01-24

    申请人： Masashi Agata ,  Hironori Akamatsu ,  Hirohito Kikukawa ,  Akihiro Sawada ,  Shunichi Iwanari

    发明人： Masashi Agata ,  Hironori Akamatsu ,  Hirohito Kikukawa ,  Akihiro Sawada ,  Shunichi Iwanari

    IPC分类号： G11C5/14

    CPC分类号： G11C5/147 ,  G11C5/143

    摘要： An external power supply voltage V.sub.CC is applied to a peripheral circuit as a first internal power supply voltage V.sub.PERI. A power supply voltage control circuit outputs a voltage control signal V.sub.SIG of a high logic level if V.sub.CC is not greater than a low limit voltage V.sub.0L in a voltage range specified by VCC recommended operating conditions, otherwise it outputs V.sub.SIG of a low logic level. A power supply circuit applies a second internal power supply voltage V.sub.W and a third internal power supply voltage V.sub.WORD to a memory cell section. V.sub.W is equal to V.sub.PERI if V.sub.SIG is HIGH, while on the other hand V.sub.W is a voltage as a result of boosting V.sub.PERI. V.sub.WORD is a voltage as a result of boosting VW to a further extent. A row decoder sends out V.sub.W onto an enable signal line of a row of sense amplifiers, and V.sub.WORD onto a word line of a memory cell array so that V.sub.W becomes a high-logic-level data write voltage to a memory cell. This adequately prolongs the data-holding time with no sacrifice in memory cell voltage resistance.

    摘要翻译： 外部电源电压VCC作为第一内部电源电压VPERI施加到外围电路。 如果VCC在VCC推荐工作条件下规定的电压范围内VCC不大于下限电压V0L，则电源电压控制电路输出高逻辑电平的电压控制信号VSIG，否则输出低逻辑电平的VSIG。 电源电路将第二内部电源电压VW和第三内部电源电压VWORD施加到存储单元部分。 如果VSIG为高电平，则VW等于VPERI，而另一方面，VW是VPERI升压的电压。 VWORD是由于将VW进一步升高而产生的电压。 行解码器将VW发送到一行读出放大器的使能信号线上，并将VWORD发送到存储单元阵列的字线上，以使VW成为存储单元的高逻辑电平数据写入电压。 这样就可以在不牺牲存储单元耐压的情况下充分延长数据保持时间。

    SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE
    27.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE 有权
    半导体存储器件和半导体器件

    公开(公告)号：US20080313391A1

    公开(公告)日：2008-12-18

    申请号：US12136340

    申请日：2008-06-10

    申请人： Shunichi Iwanari ,  Hisakazu Kotani ,  Masanori Matsuura

    发明人： Shunichi Iwanari ,  Hisakazu Kotani ,  Masanori Matsuura

    IPC分类号： G06F12/02

    CPC分类号： G11C16/26 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1063

    摘要： A semiconductor memory device, including: a cell array block including a plurality of memory cells arranged therein; and a controller, wherein the controller controls the semiconductor memory device so that: an operation of reading out data from a second region in the cell array block is initiated before completion of an operation of outputting data read out from a first region in the cell array block; and the data read out from the second region is output successively after the completion of the operation of outputting data read out from the first region.

    摘要翻译： 一种半导体存储器件，包括：包括布置在其中的多个存储单元的单元阵列块; 以及控制器，其中所述控制器控制所述半导体存储器件，使得：在完成从所述单元阵列中的第一区域读出的数据的输出的操作完成之前，开始从所述单元阵列块中的第二区域读出数据的操作 块; 在从第一区域读出的数据的输出操作完成之后连续地输出从第二区域读出的数据。

    Memory system and semiconductor integrated circuit
    28.
    发明申请
    Memory system and semiconductor integrated circuit 有权
    存储系统和半导体集成电路

    公开(公告)号：US20070279960A1

    公开(公告)日：2007-12-06

    申请号：US11878971

    申请日：2007-07-30

    申请人： Shunichi Iwanari

    发明人： Shunichi Iwanari

    IPC分类号： G11C11/22

    CPC分类号： G11C5/143 ,  G11C11/22 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50012 ,  G11C2029/0407 ,  G11C2029/5002

    摘要： A ferroelectric memory provided in a memory system stores in advance set data for data write time to memory cells. The set data include two types of data that differ between in a power-on state and in a power-off instruction time, When power is turned on, the set data that are stored in the ferroelectric memory are stored and retained in a latch circuit by a control circuit. Based on the set data retained in the latch circuit, data writing is performed in the ferroelectric memory respectively in the power-on state and in the power-off instruction time. Thus, operations of the ferroelectric memory can be controlled with desired operation timings according to operating conditions for each memory system. Excessive stress application to the ferroelectric memory during the power-on state is prevented and endurance deterioration is suppressed, while data retention characteristics after power-off are improved.

    摘要翻译： 提供在存储器系统中的铁电存储器预先存储用于数据写入时间的数据到存储器单元。 设定数据包括在通电状态和断电指令时间之间不同的两种数据。当电源接通时，存储在强电介质存储器中的设定数据被存储并保存在锁存电路中 通过控制电路。 基于保持在锁存电路中的设定数据，分别在电源接通状态和断电指示时刻的铁电存储器中进行数据写入。 因此，可以根据每个存储器系统的操作条件以期望的操作定时来控制铁电存储器的操作。 防止在通电状态下对铁电存储器施加过大的应力，并且抑制耐久性劣化，同时提高断电后的数据保持特性。

    Semiconductor memory device and semiconductor integrated device using the same
    29.
    发明授权
    Semiconductor memory device and semiconductor integrated device using the same 失效

    公开(公告)号：US06522567B2

    公开(公告)日：2003-02-18

    申请号：US09874833

    申请日：2001-06-05

    申请人： Shunichi Iwanari

    发明人： Shunichi Iwanari

    IPC分类号： G11C1122

    CPC分类号： G11C11/22

    摘要： A method and circuit are provided that can compensate for the various types of fatigue and degradation, including an imprint phenomenon, even under a variety of working conditions after a ferroelectric memory actually has been shipped as a product. The circuit includes a plurality of memory cell degradation detectors, a comparator, and a power supply circuit. Each of the memory cell degradation detectors has a plurality of data holding circuits that differ in capacitance ratio of a dummy bit line (Cb) to a dummy memory cell (Cs). The comparator compares signals from the memory cell degradation detectors to expected values. The power supply circuit changes a value of the voltage applied to the memory cell based on the signal from the comparator, provided as the result of comparison showing that the signals do not agree with the expected values. Thus, the fatigue and degradation of the ferroelectric memory cell can be detected so as to adjust the voltage to be applied to the memory cell during reading/writing.