摘要:
A method to form elevated source/drain (S/D) over staircase shaped openings in insulating layers. A gate structure is formed over a substrate. The gate structure is preferably comprised of a gate dielectric layer, gate electrode, first spacers, and hard mask. A first insulating layer is formed over the substrate and the gate structure. A resist layer is formed having an opening over the gate structure and over a lateral area adjacent to the gate structure. We etch the insulating layer through the opening in the resist layer. The etching removes a first thickness of the insulating layer to form a source/drain (S/D) opening. We remove the first spacers and hardmask to form a source/drain (S/D) contact opening. We implant ions into the substrate through the source/drain (S/D) contact opening to form lightly doped drain regions. We form second spacers on the sidewalls of the gate electrode and the gate dielectric and on the sidewalls of the insulating layer in the source/drain (S/D) contact opening and the source/drain (S/D) opening. A conductive layer is deposited over the gate electrode, the insulating layer. The conductive layer is planarized to exposed the insulating layer to form elevated source/drain (S/D) blocks on a staircase shape insulating layer.
摘要:
A new method is provided for the creation of PLDD regions that is aimed at reducing lateral p-type impurity diffusion. The process starts with a silicon substrate on the surface of which gate electrodes have been created. An NLDD implantation is performed self-aligned with the NMOS gate electrode, a layer of oxide (oxide liner) is deposited over the structure over which a layer of nitride is deposited over which a first layer of top oxide is deposited. First gate spacers are formed by etching the first layer of top oxide, stopping on the nitride layer. NS/D and PS/D implantations are performed self-aligned with respectively the NMOS and the PMOS devices, the S/D implantations are annealed. The first gate oxide spacers are removed, a PLDD implantation is performed self-aligned with the PMOS gate electrode. A second layer of top oxide is deposited over the structure and etched to form the second gate spacers on the sidewalls of the NMOS and PMOS gate electrodes. After this sequence of processing steps has been completed, the gate electrodes can be completed following conventional methods of gate electrode processing.
摘要:
A method for a vertical MOS transistor whose vertical channel width can be accurately defined and controlled. Isolation regions are formed in a substrate. The isolation regions defining an active area. Then, we form a source region in the active area. A dielectric layer is formed over the active area and the isolation regions. We form a barrier layer over the dielectric layer. We form an opening in the barrier layer. A gate layer is formed in the opening. We form an insulating layer over the conductive layer and the barrier layer. We form a gate opening through the insulating layer, the gate layer and the dielectric layer to expose the source region. Gate dielectric spacers are formed over the sidewalls of the gate layer. Then, we form a conductive plug filling the gate opening. The insulating layer is removed. We form a drain region in top and side portions of the conductive plug and form doped gate regions in the gate layer. The remaining portions of the conductive plug comprise a channel region. A channel length is between the top of the source region and the drain region. We form an interlevel dielectric layer over the barrier layer, the gate layer, and the conductive plug. Contacts are formed through the interlevel dielectric layer to the doped gate regions, the drain region and the source region.
摘要:
The invention describes three embodiments of methods for forming a balloon shaped STI trench. The first embodiment begins by forming a barrier layer over a substrate. An isolation opening is formed in the barrier layer. Next, ions are implanted into said substrate through said isolation opening to form a Si damaged or doped first region. The first region is selectively etching to form a hole. The hole is filled with an insulating material to form a balloon shaped shallow trench isolation (STI) region. The substrate has active areas between said balloon shaped shallow trench isolation (STI) regions. The second embodiment differs from the first embodiment by forming a trench in the substrate before the implant. The third embodiment forms a liner in the trench before an isotropic etch of the substrate through the trench.
摘要:
A CMOS RF device and a method to fabricate said device with low gate contact resistance are described. Conventional MOS transistor is first formed with isolation regions, poly-silicon gate structure, sidewall spacers around poly gate, and implanted source/drain with lightly and heavily doped regions. A silicon dioxide layer such as TEOS is deposited, planarized with chemical mechanical polishing (CMP) to expose the gate and treated with dilute HF etchant to recess the silicon dioxide layer below the surface of the gate. Silicon nitride is then deposited and planarized with CMP and then etched except around the gates, using a oversize poly-silicon gate mask. Inter-level dielectric mask is then deposited, contact holes etched, and contact metal is deposited to form the transistor. During contact hole etch over poly-silicon gate, silicon nitride around the poly gate acts as an etch stop. Resulting structure with direct gate contact achieves significantly reduced gate resistance and thereby improved noise performance at high frequency operation, increased unit power gain frequency (f.,), and reduced gate delay.
摘要:
A method is described to fabricate RF inductor devices on a silicon substrate. Low-k or other dielectric material is deposited and patterned to form inductor lower plate trenches. Trenches are lined with barrier film such as TaN, filled with copper, and excess metal planarized using chemical mechanical polishing (CMP). Second layer of a dielectric material is deposited and patterned to form via-hole/trenches. Via-hole/trench patterns are filled with barrier material, and the dielectric film in between the via-hole/trenches is etched to form a second set of trenches. These trenches are filled with copper and planarized. A third layer of a dielectric film is deposited and patterned to form via-hole/trenches. Via-hole/trenches are then filled with barrier material, and the dielectric film between via-hole/trench patterns etched to form a third set of trenches. These trenches are filled with copper metal and excess metal removed by CMP to form said RF inductor.
摘要:
An apparatus for preventing distortion to critical dimension line images formed by a SEM under the influence of external electro-magnetic emissions generating by neighboring manufacturing equipment. The external emission causes a high three sigma A/C component. The correcting apparatus includes an external shielding coil mounted to the column housing of the SEM. A control electro-emission driver is mounted to the external shielding coil in which a variable voltage divider having a transformer with a variable resistor. The variable resistor is adjusted varying the amplitude of the sine wave of the A/C signal thus controlling the electro-emission driver while reducing the effects of the three sigma A/C component.
摘要:
A method for forming a transistor having low overlap capacitance by forming a microtrench at the gate edge to reduce effective dielectric constant is described. A gate electrode is provided overlying a gate dielectric layer on a substrate and having a hard mask layer thereover. An oxide layer is formed overlying the substrate. First spacers are formed on sidewalls of the gate electrode and overlying the oxide layer. Source/drain extensions are implanted. Second spacers are formed on the first spacers. Source/drain regions are implanted. A dielectric layer is deposited overlying the gate electrode and the oxide layer and planarized to the hard mask layer whereby the first and second spacers are exposed. The exposed second spacers and underlying oxide layer are removed. The exposed substrate underlying the second spacers is etched into to form a microtrench undercutting the gate oxide layer at an edge of the gate electrode. The microtrench is filled with an epitaxial oxide layer and planarized to the hard mask layer. The dielectric layer is patterned to form third spacers on the epitaxial oxide layer. The microtrench reduces the effective dielectric constant at the overlap between the gate and the source/drain extensions to complete formation of a transistor having low overlap capacitance.
摘要:
A method for forming a gate dielectric having regions with different dielectric constants. A dummy dielectric layer is formed over a semiconductor structure. The dummy dielectric layer is patterned to form a gate opening. A high-K dielectric layer is formed over the dummy dielectric and in the gate opening. A low-K dielectric layer is formed on the high-K dielectric layer. Spacers are formed on the low-K dielectric layer at the edges of the gate opening. The low-K dielectric layer is removed from the bottom of the gate opening between the spacers. The spacers are removed to form a stepped gate opening. The stepped gate opening has both a high-K dielectric layer and a low-K dielectric layer on the sidewalls and at the edges of the bottom of the gate opening and only a high-k dielectric layer in the center of the bottom of the stepped gate opening. A gate electrode is formed in the stepped gate opening.
摘要:
A method for forming an L-shaped spacer using disposable polysilicon top spacers. A semiconductor structure is provided having a gate structure thereon. A liner oxide layer is formed on the gate structure. A dielectric spacer layer is formed on the liner oxide layer. A disposable polysilicon top spacer layer is formed on the dielectric spacer layer. The disposable polysilicon top spacer layer is anisotropically etched to form disposable polysilicon top spacers. The dielectric spacer layer is etched to form L-shaped dielectric spacers, using the disposable polysilicon top spacers as an etch mask. The disposable polysilicon top spacers are removed leaving an L-shaped dielectric spacer. In one embodiment, lightly doped source and drain regions are formed prior to forming the liner oxide layer and the L-shaped spacers.