Method to form self-aligned source/drain CMOS device on insulated staircase oxide
    21.
    发明授权
    Method to form self-aligned source/drain CMOS device on insulated staircase oxide 失效
    在绝缘阶梯氧化物上形成自对准源极/漏极CMOS器件的方法

    公开(公告)号:US06541327B1

    公开(公告)日:2003-04-01

    申请号:US09760123

    申请日:2001-01-16

    IPC分类号: H01L218238

    摘要: A method to form elevated source/drain (S/D) over staircase shaped openings in insulating layers. A gate structure is formed over a substrate. The gate structure is preferably comprised of a gate dielectric layer, gate electrode, first spacers, and hard mask. A first insulating layer is formed over the substrate and the gate structure. A resist layer is formed having an opening over the gate structure and over a lateral area adjacent to the gate structure. We etch the insulating layer through the opening in the resist layer. The etching removes a first thickness of the insulating layer to form a source/drain (S/D) opening. We remove the first spacers and hardmask to form a source/drain (S/D) contact opening. We implant ions into the substrate through the source/drain (S/D) contact opening to form lightly doped drain regions. We form second spacers on the sidewalls of the gate electrode and the gate dielectric and on the sidewalls of the insulating layer in the source/drain (S/D) contact opening and the source/drain (S/D) opening. A conductive layer is deposited over the gate electrode, the insulating layer. The conductive layer is planarized to exposed the insulating layer to form elevated source/drain (S/D) blocks on a staircase shape insulating layer.

    摘要翻译: 一种在绝缘层中的阶梯形开口形成升高的源极/漏极(S / D)的方法。 栅极结构形成在衬底上。 栅极结构优选由栅极电介质层,栅电极,第一间隔物和硬掩模组成。 在衬底和栅极结构之上形成第一绝缘层。 形成抗蚀剂层,其具有在栅极结构上方的开口以及与栅极结构相邻的横向区域。 我们通过抗蚀剂层中的开口蚀刻绝缘层。 蚀刻去除绝缘层的第一厚度以形成源极/漏极(S / D)开口。 我们移除第一个垫片和硬掩模以形成一个源极/漏极(S / D)接触开口。 我们通过源极/漏极(S / D)接触开口将离子注入到衬底中,以形成轻掺杂的漏极区。 我们在源极/漏极(S / D)接触开口和源极/漏极(S / D)开口中的栅电极和栅极电介质的侧壁和绝缘层的侧壁上形成第二间隔物。 在栅电极,绝缘层上沉积导电层。 导电层被平坦化以暴露绝缘层,以在阶梯形绝缘层上形成升高的源极/漏极(S / D)块。

    Method for forming PLDD structure with minimized lateral dopant diffusion
    22.
    发明授权
    Method for forming PLDD structure with minimized lateral dopant diffusion 有权
    用最小化横向掺杂剂扩散形成PLDD结构的方法

    公开(公告)号:US06451704B1

    公开(公告)日:2002-09-17

    申请号:US09849672

    申请日:2001-05-07

    IPC分类号: H01L2100

    摘要: A new method is provided for the creation of PLDD regions that is aimed at reducing lateral p-type impurity diffusion. The process starts with a silicon substrate on the surface of which gate electrodes have been created. An NLDD implantation is performed self-aligned with the NMOS gate electrode, a layer of oxide (oxide liner) is deposited over the structure over which a layer of nitride is deposited over which a first layer of top oxide is deposited. First gate spacers are formed by etching the first layer of top oxide, stopping on the nitride layer. NS/D and PS/D implantations are performed self-aligned with respectively the NMOS and the PMOS devices, the S/D implantations are annealed. The first gate oxide spacers are removed, a PLDD implantation is performed self-aligned with the PMOS gate electrode. A second layer of top oxide is deposited over the structure and etched to form the second gate spacers on the sidewalls of the NMOS and PMOS gate electrodes. After this sequence of processing steps has been completed, the gate electrodes can be completed following conventional methods of gate electrode processing.

    摘要翻译: 提供了一种用于创建旨在减少横向p型杂质扩散的PLDD区域的新方法。 该工艺从在其上形成栅电极的表面上的硅衬底开始。 执行NIGD注入与NMOS栅电极自对准,一层氧化物(氧化物衬垫)沉积在其上沉积有一层氮化物的结构上,第一层顶层氧化物沉积在该层上。 通过蚀刻顶部氧化物的第一层,停止在氮化物层上形成第一栅极间隔物。 NS / D和PS / D注入分别与NMOS和PMOS器件自对准,S / D注入退火。 去除第一栅极氧化物间隔物,执行PLDD注入与PMOS栅电极自对准。 在结构上沉积第二层顶部氧化物,并被蚀刻以在NMOS和PMOS栅电极的侧壁上形成第二栅极间隔物。 在该处理步骤顺序完成之后,可以按照常规的栅电极处理方法来完成栅电极。

    Method to control the channel length of a vertical transistor by first forming channel using selective epi and source/drain using implantation
    23.
    发明授权
    Method to control the channel length of a vertical transistor by first forming channel using selective epi and source/drain using implantation 失效
    通过使用选择性外延和使用注入的源极/漏极首先形成沟道来控制垂直晶体管的沟道长度的方法

    公开(公告)号:US06436770B1

    公开(公告)日:2002-08-20

    申请号:US09721720

    申请日:2000-11-27

    IPC分类号: H01L21332

    摘要: A method for a vertical MOS transistor whose vertical channel width can be accurately defined and controlled. Isolation regions are formed in a substrate. The isolation regions defining an active area. Then, we form a source region in the active area. A dielectric layer is formed over the active area and the isolation regions. We form a barrier layer over the dielectric layer. We form an opening in the barrier layer. A gate layer is formed in the opening. We form an insulating layer over the conductive layer and the barrier layer. We form a gate opening through the insulating layer, the gate layer and the dielectric layer to expose the source region. Gate dielectric spacers are formed over the sidewalls of the gate layer. Then, we form a conductive plug filling the gate opening. The insulating layer is removed. We form a drain region in top and side portions of the conductive plug and form doped gate regions in the gate layer. The remaining portions of the conductive plug comprise a channel region. A channel length is between the top of the source region and the drain region. We form an interlevel dielectric layer over the barrier layer, the gate layer, and the conductive plug. Contacts are formed through the interlevel dielectric layer to the doped gate regions, the drain region and the source region.

    摘要翻译: 一种垂直MOS晶体管的方法,其垂直沟道宽度可以被精确地限定和控制。 在衬底中形成隔离区。 隔离区限定有效区域。 然后,我们在活动区域​​中形成一个源区域。 在有源区域和隔离区域上形成介电层。 我们在电介质层上形成阻挡层。 我们在屏障层形成一个开口。 在开口中形成栅极层。 我们在导电层和阻挡层上形成绝缘层。 我们通过绝缘层,栅极层和电介质层形成栅极开口以暴露源极区域。 栅极电介质隔离物形成在栅极层的侧壁上。 然后,我们形成一个填充门开口的导电塞。 绝缘层被去除。 我们在导电插塞的顶部和侧部形成漏极区,并在栅极层中形成掺杂的栅极区。 导电插塞的其余部分包括沟道区域。 沟道长度在源极区域的顶部和漏极区域之间。 我们在阻挡层,栅极层和导电插塞上形成层间电介质层。 通过层间介质层与掺杂栅极区,漏极区和源极区形成触点。

    Method to form a balloon shaped STI using a micro machining technique to remove heavily doped silicon
    24.
    发明授权
    Method to form a balloon shaped STI using a micro machining technique to remove heavily doped silicon 失效
    使用微加工技术形成气球形STI以去除重掺杂硅的方法

    公开(公告)号:US06313008B1

    公开(公告)日:2001-11-06

    申请号:US09768486

    申请日:2001-01-25

    IPC分类号: H01L2176

    CPC分类号: H01L21/76232

    摘要: The invention describes three embodiments of methods for forming a balloon shaped STI trench. The first embodiment begins by forming a barrier layer over a substrate. An isolation opening is formed in the barrier layer. Next, ions are implanted into said substrate through said isolation opening to form a Si damaged or doped first region. The first region is selectively etching to form a hole. The hole is filled with an insulating material to form a balloon shaped shallow trench isolation (STI) region. The substrate has active areas between said balloon shaped shallow trench isolation (STI) regions. The second embodiment differs from the first embodiment by forming a trench in the substrate before the implant. The third embodiment forms a liner in the trench before an isotropic etch of the substrate through the trench.

    摘要翻译: 本发明描述了形成球形STI沟槽的方法的三个实施例。 第一实施例开始于在衬底上形成阻挡层。 在阻挡层中形成隔离开口。 接下来,通过所述隔离开口将离子注入到所述衬底中,以形成Si损伤或掺杂的第一区域。 第一区域是选择性蚀刻以形成孔。 孔用绝缘材料填充以形成气球形的浅沟槽隔离(STI)区域。 衬底在所述球形浅沟槽隔离(STI)区域之间具有有效区域。 第二实施例通过在植入物之前在衬底中形成沟槽而与第一实施例不同。 在通过沟槽对衬底进行各向同性蚀刻之前,第三实施例在沟槽中形成衬垫。

    METHOD OF MAKING DIRECT CONTACT ON GATE BY USING DIELECTRIC STOP LAYER
    25.
    发明申请
    METHOD OF MAKING DIRECT CONTACT ON GATE BY USING DIELECTRIC STOP LAYER 失效
    通过使用介质停止层在门上制造直接接触的方法

    公开(公告)号:US20050059216A1

    公开(公告)日:2005-03-17

    申请号:US10664211

    申请日:2003-09-17

    CPC分类号: H01L21/76802 H01L21/76829

    摘要: A CMOS RF device and a method to fabricate said device with low gate contact resistance are described. Conventional MOS transistor is first formed with isolation regions, poly-silicon gate structure, sidewall spacers around poly gate, and implanted source/drain with lightly and heavily doped regions. A silicon dioxide layer such as TEOS is deposited, planarized with chemical mechanical polishing (CMP) to expose the gate and treated with dilute HF etchant to recess the silicon dioxide layer below the surface of the gate. Silicon nitride is then deposited and planarized with CMP and then etched except around the gates, using a oversize poly-silicon gate mask. Inter-level dielectric mask is then deposited, contact holes etched, and contact metal is deposited to form the transistor. During contact hole etch over poly-silicon gate, silicon nitride around the poly gate acts as an etch stop. Resulting structure with direct gate contact achieves significantly reduced gate resistance and thereby improved noise performance at high frequency operation, increased unit power gain frequency (f.,), and reduced gate delay.

    摘要翻译: 描述CMOS RF器件和制造具有低栅极接触电阻的所述器件的方法。 传统的MOS晶体管首先形成有隔离区域,多晶硅栅极结构,围绕多晶硅栅极的侧壁隔离物以及具有轻掺杂和重掺杂区域的注入源极/漏极。 沉积诸如TEOS的二氧化硅层,通过化学机械抛光(CMP)平坦化以暴露栅极,并用稀的HF蚀刻剂处理以使位于栅极表面下方的二氧化硅层凹陷。 然后将氮化硅沉积并用CMP平坦化,然后使用超大型多晶硅栅极掩模在栅极周围进行蚀刻。 然后沉积层间电介质掩模,蚀刻接触孔,并沉积接触金属以形成晶体管。 在多晶硅栅极的接触孔蚀刻期间,多晶硅周围的氮化硅作为蚀刻停止。 具有直接栅极接触的所得结构实现了显着降低的栅极电阻,从而改善了高频操作时的噪声性能,增加的单位功率增益频率(f。)和减小的栅极延迟。

    Image compensation device for a scanning electron microscope
    27.
    发明授权
    Image compensation device for a scanning electron microscope 有权
    用于扫描电子显微镜的图像补偿装置

    公开(公告)号:US06791083B2

    公开(公告)日:2004-09-14

    申请号:US10207551

    申请日:2002-07-29

    IPC分类号: G01N2300

    CPC分类号: H01J37/09 H01J2237/28

    摘要: An apparatus for preventing distortion to critical dimension line images formed by a SEM under the influence of external electro-magnetic emissions generating by neighboring manufacturing equipment. The external emission causes a high three sigma A/C component. The correcting apparatus includes an external shielding coil mounted to the column housing of the SEM. A control electro-emission driver is mounted to the external shielding coil in which a variable voltage divider having a transformer with a variable resistor. The variable resistor is adjusted varying the amplitude of the sine wave of the A/C signal thus controlling the electro-emission driver while reducing the effects of the three sigma A/C component.

    摘要翻译: 一种用于在由相邻制造设备产生的外部电磁发射的影响下由SEM形成的临界尺寸线图像的变形的装置。 外部发射导致高三西格玛A / C分量。 校正装置包括安装在扫描电镜的柱壳体上的外部屏蔽线圈。 控制发光驱动器安装到外部屏蔽线圈,其中具有变压器的可变分压器具有可变电阻器。 调节可变电阻器改变A / C信号的正弦波的振幅,从而控制电发射驱动器,同时减少三西格玛A / C分量的影响。

    Method to form low-overlap-capacitance transistors by forming microtrench at the gate edge
    28.
    发明授权
    Method to form low-overlap-capacitance transistors by forming microtrench at the gate edge 失效
    通过在栅极边缘形成微动开关来形成低重叠电容晶体管的方法

    公开(公告)号:US06417056B1

    公开(公告)日:2002-07-09

    申请号:US09981439

    申请日:2001-10-18

    IPC分类号: H01L21336

    摘要: A method for forming a transistor having low overlap capacitance by forming a microtrench at the gate edge to reduce effective dielectric constant is described. A gate electrode is provided overlying a gate dielectric layer on a substrate and having a hard mask layer thereover. An oxide layer is formed overlying the substrate. First spacers are formed on sidewalls of the gate electrode and overlying the oxide layer. Source/drain extensions are implanted. Second spacers are formed on the first spacers. Source/drain regions are implanted. A dielectric layer is deposited overlying the gate electrode and the oxide layer and planarized to the hard mask layer whereby the first and second spacers are exposed. The exposed second spacers and underlying oxide layer are removed. The exposed substrate underlying the second spacers is etched into to form a microtrench undercutting the gate oxide layer at an edge of the gate electrode. The microtrench is filled with an epitaxial oxide layer and planarized to the hard mask layer. The dielectric layer is patterned to form third spacers on the epitaxial oxide layer. The microtrench reduces the effective dielectric constant at the overlap between the gate and the source/drain extensions to complete formation of a transistor having low overlap capacitance.

    摘要翻译: 描述了通过在栅极边缘处形成微通孔以形成具有低重叠电容的晶体管以降低有效介电常数的方法。 栅电极被设置在衬底上的栅介电层上,并且在其上具有硬掩模层。 在衬底上形成氧化物层。 第一间隔物形成在栅电极的侧壁上并覆盖氧化物层。 源/漏扩展被植入。 第二间隔件形成在第一间隔件上。 源极/漏极区域被植入。 沉积覆盖在栅电极和氧化物层上的介电层,并且平坦化到硬掩模层,由此使第一和第二间隔物暴露。 去除暴露的第二间隔物和下面的氧化物层。 蚀刻第二间隔物下面的暴露的基底以形成在栅电极的边缘处切割栅极氧化物层的微切口。 微通孔填充有外延氧化物层并且平坦化到硬掩模层。 图案化电介质层以在外延氧化物层上形成第三间隔物。 微通道减小栅极和源极/漏极延伸部之间的重叠处的有效介电常数,以完成具有低重叠电容的晶体管的形成。

    Method for forming a transistor gate dielectric with high-K and low-K regions
    29.
    发明授权
    Method for forming a transistor gate dielectric with high-K and low-K regions 有权
    用于形成具有高K和低K区的晶体管栅极电介质的方法

    公开(公告)号:US06406945B1

    公开(公告)日:2002-06-18

    申请号:US09769810

    申请日:2001-01-26

    IPC分类号: H01L21335

    摘要: A method for forming a gate dielectric having regions with different dielectric constants. A dummy dielectric layer is formed over a semiconductor structure. The dummy dielectric layer is patterned to form a gate opening. A high-K dielectric layer is formed over the dummy dielectric and in the gate opening. A low-K dielectric layer is formed on the high-K dielectric layer. Spacers are formed on the low-K dielectric layer at the edges of the gate opening. The low-K dielectric layer is removed from the bottom of the gate opening between the spacers. The spacers are removed to form a stepped gate opening. The stepped gate opening has both a high-K dielectric layer and a low-K dielectric layer on the sidewalls and at the edges of the bottom of the gate opening and only a high-k dielectric layer in the center of the bottom of the stepped gate opening. A gate electrode is formed in the stepped gate opening.

    摘要翻译: 一种形成具有不同介电常数区域的栅极电介质的方法。 在半导体结构上形成虚拟电介质层。 图案化虚拟介质层以形成栅极开口。 在虚拟电介质上和栅极开口中形成高K电介质层。 在高K电介质层上形成低K电介质层。 在栅极开口边缘的低K电介质层上形成间隔物。 低K电介质层从间隔物之间​​的栅极开口的底部去除。 移除间隔件以形成阶梯式门开口。 阶梯式门开口在侧壁和栅极开口底部的边缘处具有高K电介质层和低K电介质层,并且仅在台阶底部中心的高k电介质层 开门 在阶梯式门开口形成栅电极。

    Method for forming an L-shaped spacer using a disposable polysilicon spacer
    30.
    发明授权
    Method for forming an L-shaped spacer using a disposable polysilicon spacer 有权
    使用一次性多晶硅间隔物形成L形间隔物的方法

    公开(公告)号:US06346468B1

    公开(公告)日:2002-02-12

    申请号:US09502037

    申请日:2000-02-11

    IPC分类号: H01L213205

    摘要: A method for forming an L-shaped spacer using disposable polysilicon top spacers. A semiconductor structure is provided having a gate structure thereon. A liner oxide layer is formed on the gate structure. A dielectric spacer layer is formed on the liner oxide layer. A disposable polysilicon top spacer layer is formed on the dielectric spacer layer. The disposable polysilicon top spacer layer is anisotropically etched to form disposable polysilicon top spacers. The dielectric spacer layer is etched to form L-shaped dielectric spacers, using the disposable polysilicon top spacers as an etch mask. The disposable polysilicon top spacers are removed leaving an L-shaped dielectric spacer. In one embodiment, lightly doped source and drain regions are formed prior to forming the liner oxide layer and the L-shaped spacers.

    摘要翻译: 一种使用一次性多晶硅顶部间隔物形成L形间隔件的方法。 提供其上具有栅极结构的半导体结构。 在栅极结构上形成衬里氧化物层。 介电间隔层形成在衬垫氧化物层上。 一次性多晶硅顶部间隔层形成在电介质间隔层上。 一次性多晶硅顶部间隔层被各向异性蚀刻以形成一次性多晶硅顶部间隔物。 使用一次性多晶硅顶部间隔物作为蚀刻掩模,蚀刻电介质间隔层以形成L形电介质间隔物。 去除一次性多晶硅顶部间隔物,留下L形介电间隔物。 在一个实施例中,在形成衬垫氧化物层和L形间隔物之前形成轻掺杂的源极和漏极区。