公开(公告)号：US20080079059A1

公开(公告)日：2008-04-03

申请号：US11789471

申请日：2007-04-20

Applicant: Yider Wu

Inventor： Yider Wu

IPC: H01L29/76 ,  H01L21/336

CPC classification number: H01L29/78 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isolate stripe-shaped element-forming regions. Formed on the substrate area floating gate via a first gate insulating film and further a control gate via a second gate insulating film. Source and drain diffusion layers are formed in self-alignment with control gates. The second gate insulating film on the floating gate is divided and separated together with the floating gate by slits above the element isolation/insulation films into discrete portions of individual memory cells. The select gate is formed with a STI recess process in advance locally in the select area.

Abstract translation: 旨在防止由浮动栅极之间的电荷的移动引起的数据破坏，从而提高可靠性的非易失性半导体存储器件包括埋入硅衬底中以隔离条形元件形成区域的元件隔离/绝缘膜。 经由第一栅极绝缘膜形成在衬底区域浮动栅极上，并且还经由第二栅极绝缘膜形成控制栅极。 源极和漏极扩散层与控制栅极自对准地形成。 浮动栅极上的第二栅极绝缘膜通过在元件隔离/绝缘膜上方的狭缝与浮动栅极分开并分离成各个存储单元的离散部分。 选择门在选择区域中局部地预先形成有STI凹陷处理。

公开(公告)号：US20070259493A1

公开(公告)日：2007-11-08

申请号：US11745059

申请日：2007-05-07

Applicant: KENT KUOHUA CHANG ,  Jongoh Kim ,  Yider Wu

Inventor： KENT KUOHUA CHANG ,  Jongoh Kim ,  Yider Wu

IPC: H01L21/8234

CPC classification number: H01L27/11568 ,  H01L27/105 ,  H01L27/11573

Abstract: A method of fabricating a memory device is described. During the process of forming the memory cell area and the periphery area of a semiconductor device a photoresist layer is formed on the memory cell area before the spacers are formed on the sidewalls of the gates. Therefore, the memory cell area is prevented from being damaged to mitigate the leakage current problem during the process of forming spacers in the periphery circuit area.

Abstract translation: 描述了一种制造存储器件的方法。 在形成存储单元区域和半导体器件的外围区域的过程中，在形成在栅极的侧壁上的间隔物之前，在存储单元区域上形成光致抗蚀剂层。 因此，在外围电路区域中形成间隔物的过程中，防止存储单元区域被损坏以减轻漏电流问题。

公开(公告)号：US06737701B1

公开(公告)日：2004-05-18

申请号：US10313454

申请日：2002-12-05

Applicant: Amy C. Tu ,  Jean Yee-Mei Yang ,  Yider Wu

Inventor： Amy C. Tu ,  Jean Yee-Mei Yang ,  Yider Wu

IPC: H01L31119

CPC classification number: H01L27/11568 ,  H01L27/115

Abstract: According to one exemplary embodiment, a structure comprises a first bit line and a second bit line. The structure further comprises a first memory cell situated over the first bit line, where the first memory cell comprises a first ONO stack segment, and where the first ONO stack segment is situated between the first bit line and a word line. The structure further comprises a second memory cell situated over the second bit line, where the second memory cell comprises a second ONO stack segment, where the second ONO stack segment is situated between the second bit line and the word line, and where the first ONO stack segment is separated from the second ONO stack segment by a gap. The first memory cell and the second memory cell may each be capable, for example, of storing two independent data bits.

Abstract translation: 根据一个示例性实施例，一种结构包括第一位线和第二位线。 该结构还包括位于第一位线之上的第一存储器单元，其中第一存储器单元包括第一ONO堆栈段，并且其中第一ONO堆栈段位于第一位线和字线之间。 该结构还包括位于第二位线之上的第二存储器单元，其中第二存储器单元包括第二ONO堆栈段，其中第二ONO堆栈段位于第二位线和字线之间，并且其中第一ONO 堆叠段与第二ONO堆栈段间隔开。 第一存储器单元和第二存储单元可以各自能够例如存储两个独立的数据位。

公开(公告)号：US06707078B1

公开(公告)日：2004-03-16

申请号：US10230729

申请日：2002-08-29

Applicant: Hidehiko Shiraiwa ,  Yider Wu ,  Jean Yee-Mei Yang ,  Mark T. Ramsbey ,  Darlene G. Hamilton

Inventor： Hidehiko Shiraiwa ,  Yider Wu ,  Jean Yee-Mei Yang ,  Mark T. Ramsbey ,  Darlene G. Hamilton

IPC: H01L2968

CPC classification number: H01L27/11568 ,  G11C16/0466 ,  H01L27/115

Abstract: One aspect of the present invention relates to a SONOS type non-volatile semiconductor memory device having improved erase speed, the device containing bitlines extending in a first direction; wordlines extending in a second direction, the wordlines comprising functioning wordlines and at least one dummy wordline, wherein the dummy wordline is positioned near at least one of a bitline contact and an edge of the core region, and the dummy wordline is treated so as not to cycle between on and off states. Another aspect of the present invention relates to a method of making a SONOS type non-volatile semiconductor memory device having improved erase speed, involving forming a plurality of bitlines extending in a first direction in the core region; forming a plurality of functioning wordlines extending in a second direction in the core region; forming at least one dummy wordline between the functioning wordlines and the periphery region or between the functioning wordlines and a bitline contact and treating the device so that the dummy wordline does not cycle between on and off states.

Abstract translation: 本发明的一个方面涉及一种具有改进的擦除速度的SONOS型非易失性半导体存储器件，该器件含有沿第一方向延伸的位线; 所述字线在第二方向上延伸，所述字线包括功能字线和至少一个伪字线，其中所述伪字线位于所述芯区域的位线接触和边缘中的至少一个附近，并且所述伪字线被处理为不 在开关状态之间循环。 本发明的另一方面涉及一种制造具有改进的擦除速度的SONOS型非易失性半导体存储器件的方法，包括形成在芯区域中沿第一方向延伸的多个位线; 形成在所述芯区域中沿第二方向延伸的多个功能字线; 在功能字线和外围区域之间或在功能字线和位线接触之间形成至少一个伪字线，并对器件进行处理，使得伪字线不会在导通和关断状态之间循环。

公开(公告)号：US06680509B1

公开(公告)日：2004-01-20

申请号：US10158044

申请日：2002-05-30

Applicant: Yider Wu ,  Jean Yee-Mei Yang ,  Mark Ramsbey ,  Emmanuel H. Lingunis ,  Yu Sun

Inventor： Yider Wu ,  Jean Yee-Mei Yang ,  Mark Ramsbey ,  Emmanuel H. Lingunis ,  Yu Sun

IPC: H01L29792

CPC classification number: H01L27/11568 ,  H01L27/115 ,  Y10S438/954

Abstract: A method for fabricating a SONOS device having a buried bit-line including the steps of: providing a semiconductor substrate having an ONO structure overlying the semiconductor substrate; forming a nitride barrier layer on the ONO structure to form, a four-layer stack; forming a patterned photoresist layer on the nitride barrier layer; implanting As or P ions through the four-layer stack to form a bit-line buried under the ONO structure; stripping the photoresist layer and cleaning an upper surface of the four-layer stack; and consolidating the four-layer stack by applying an oxidation cycle. The invention further relates to a SONOS-type device including the nitride barrier layer.

Abstract translation: 一种用于制造具有掩埋位线的SONOS器件的方法，包括以下步骤：提供具有覆盖在半导体衬底上的ONO结构的半导体衬底; 在ONO结构上形成氮化物阻挡层以形成四层堆叠; 在氮化物阻挡层上形成图案化的光致抗蚀剂层; 将As或P离子注入四层堆叠中以形成埋在ONO结构下的位线; 剥离光致抗蚀剂层并清洁四层堆叠的上表面; 并通过施加氧化循环来合并四层堆叠。 本发明还涉及包括氮化物阻挡层的SONOS型器件。

公开(公告)号：US06664191B1

公开(公告)日：2003-12-16

申请号：US09973131

申请日：2001-10-09

Applicant: Unsoon Kim ,  Yider Wu ,  Yu Sun ,  Michael K. Templeton ,  Angela T. Hui ,  Chi Chang

Inventor： Unsoon Kim ,  Yider Wu ,  Yu Sun ,  Michael K. Templeton ,  Angela T. Hui ,  Chi Chang

IPC: H01L21302

CPC classification number: H01L27/11526 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76229 ,  H01L21/76838 ,  H01L27/11531 ,  Y10S438/975

Abstract: A method is provided of forming lines with spaces between memory cells below a minimum printing dimension of a photolithographic tool set. In one aspect of the invention, lines and spaces are formed in a first polysilicon layer that forms floating gates of flash memory cells. STI regions are formed between adjacent memory cells in a substrate to isolate the cells from one another. The first polysilicon layer is deposited over the substrate covering the STI regions. The first polysilicon layer is then planarized by a CMP process or the like to eliminate overlay issues associated with the STI regions. A hard mask layer is deposited over the first polysilicon layer and a first space dimension d1 etched between adjacent memory cells. A conformal nitride layer is deposited over the hard mask layer and an etch step performed to form nitride side walls adjacent the spaces. The nitride side walls reduce the first space dimension to a second space dimension d2, so that spaces can be formed in the first polysilicon layer at a dimension smaller than the minimum printable dimension of the photolithographic tool set.

Abstract translation: 提供了一种在光刻工具组的最小打印尺寸之下形成具有在存储器单元之间的空间的线的方法。 在本发明的一个方面，线和间隔形成在形成闪存单元的浮动栅极的第一多晶硅层中。 STI区域形成在衬底中的相邻存储单元之间，以隔离细胞。 第一多晶硅层沉积在覆盖STI区域的衬底上。 然后通过CMP工艺等将第一多晶硅层平坦化，以消除与STI区域相关联的覆盖问题。 在第一多晶硅层上沉积硬掩模层，并在相邻的存储单元之间蚀刻第一空间尺寸d1。 在硬掩模层上沉积共形氮化物层，并且执行蚀刻步骤以形成邻近空间的氮化物侧壁。 氮化物侧壁将第一空间尺寸减小到第二空间尺寸d2，使得可以以小于光刻工具组的最小可打印尺寸的尺寸在第一多晶硅层中形成空间。

公开(公告)号：US06566736B1

公开(公告)日：2003-05-20

申请号：US09998624

申请日：2001-11-30

Applicant: Hiroyuki Ogawa ,  Yider Wu ,  Yu Sun

Inventor： Hiroyuki Ogawa ,  Yider Wu ,  Yu Sun

IPC: H01L23544

CPC classification number: H01L23/564 ,  H01L23/3185 ,  H01L23/485 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05567 ,  H01L2224/45144 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Moisture seal apparatus and methodologies are disclosed for protecting semiconductor devices from moisture. An upper seal layer, such as SiN is formed over an upper insulator layer and an exposed portion of a die seal metal structure so as to form a vertical moisture seal between electrical components in the semiconductor device and the ambient environment. A lateral seal may be formed from the die seal metal structure in an upper metal layer in the device and one or more contacts extending downward from the die seal metal to the substrate or to a lower die seal metal structure.

Abstract translation: 公开了用于保护半导体器件免受湿气的湿度密封装置和方法。 在上绝缘体层和模具密封金属结构的暴露部分上形成诸如SiN的上密封层，以便在半导体器件中的电气部件和周围环境之间形成垂直的湿气密封。 横向密封件可以由装置中的上金属层中的模具密封金属结构和从模具密封金属向下延伸到基板或下模密封金属结构的一个或多个触点形成。

公开(公告)号：US08802537B1

公开(公告)日：2014-08-12

申请号：US11189874

申请日：2005-07-27

Applicant: Yider Wu ,  Unsoon Kim ,  Kuo-Tung Chang ,  Harpreet Sachar

Inventor： Yider Wu ,  Unsoon Kim ,  Kuo-Tung Chang ,  Harpreet Sachar

IPC: H01L21/76

CPC classification number: H01L21/76224 ,  H01L21/02057

Abstract: A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The memory device is pre-cleaned to prepare a surface of the memory device for oxide formation thereon, where cleaning the memory device removes portions of the barrier oxide layer on opposite sides of the trench. The nitride layer is trimmed on opposite sides of the trench. A liner oxide layer is formed in the trench.

Abstract translation: 提供了一种用于形成存储器件的方法。 在衬底上形成氮化物层。 蚀刻氮化物层和衬底以形成沟槽。 存储器件被预先清洁以准备用于其上形成氧化物的存储器件的表面，其中清洁存储器件去除沟槽相对侧上的阻挡氧化物层的部分。 在沟槽的相对侧上修整氮化物层。 在沟槽中形成衬里氧化物层。

公开(公告)号：US08476156B1

公开(公告)日：2013-07-02

申请号：US13338405

申请日：2011-12-28

Applicant: Yider Wu ,  Hung-Wei Chen

Inventor： Yider Wu ,  Hung-Wei Chen

IPC: H01L21/3205 ,  H01L21/4763

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/7881

Abstract: In a manufacturing method of a flash memory structure with a stress area, a better stress effect can be achieved by controlling the manufacturing process of a tunneling oxide layer formed in a gate structure and contacted with a silicon substrate, so that an L-shaped spacer (or a first stress area) and a contact etch stop layer (or a second stress area) of each L-shaped spacer are formed between two gate structures and aligned towards each other to enhance the carrier mobility of the gate structure, so as to achieve the effects of improving a read current, obtaining the required read current by using a lower read voltage, reducing the possibility of having a stress-induced leakage current, and enhancing the data preservation of the flash memory.

Abstract translation: 在具有应力区域的闪存结构的制造方法中，通过控制形成在栅极结构中并与硅衬底接触的隧道氧化物层的制造工艺，可以获得更好的应力效应，使得L形间隔物 （或第一应力区域）和每个L形间隔物的接触蚀刻停止层（或第二应力区域）形成在两个栅极结构之间并且彼此对准以增强栅极结构的载流子迁移率，从而 实现改善读取电流的效果，通过使用较低的读取电压获得所需的读取电流，减少产生应力引起的漏电流的可能性，以及增强闪速存储器的数据保存。

公开(公告)号：US07939423B2

公开(公告)日：2011-05-10

申请号：US12761460

申请日：2010-04-16

Applicant: Yider Wu

Inventor： Yider Wu

IPC: H01L21/76

CPC classification number: H01L29/78 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A non-volatile semiconductor manufacturing method comprises the steps of making element isolation/insulation films that partitions element-forming regions in a semiconductor substrate; stacking a floating gate on the semiconductor substrate via a first gate insulating film; stacking a second gate insulating film formed on the floating gate, and stacking a control gate formed on the floating gate via the second gate insulating film, and self-aligning source and drain diffusion area with the control gate. In the process of stacking a floating gate by partially etching a field oxide film in a select gate area, followed by floating gate formed in a element-forming region and select gate region, and followed by a chemical mechanical polish(CMP) process, both floating gate and select gate is hereby formed simultaneously. Thereby, when memory cells are miniaturized, the invention allows the process to be simple and reduce the defect density.

Abstract translation: 非易失性半导体制造方法包括以下步骤：制造在半导体衬底中分隔元件形成区域的元件隔离/绝缘膜; 通过第一栅极绝缘膜在半导体衬底上堆叠浮置栅极; 堆叠形成在浮置栅极上的第二栅极绝缘膜，并且通过第二栅极绝缘膜堆叠形成在浮置栅极上的控制栅极以及与控制栅极的自对准源极和漏极扩散区域。 在通过在选择栅极区域中局部蚀刻场氧化物膜的同时堆叠浮栅的过程中，随后是形成在元件形成区域中的浮栅并选择栅极区域，然后进行化学机械抛光（CMP）工艺， 浮动门和选择门同时形成。 因此，当存储单元小型化时，本发明允许该过程简单并减少缺陷密度。