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113 条记录 (耗时 0.037 秒)

    Semiconductor integrated circuit device and method of manufacturing the same
    22.
    发明授权
    Semiconductor integrated circuit device and method of manufacturing the same 有权
    半导体集成电路器件及其制造方法

    公开(公告)号：US06770527B2

    公开(公告)日：2004-08-03

    申请号：US10294712

    申请日：2002-11-15

    申请人： Shoji Shukuri ,  Kenichi Kuroda

    发明人： Shoji Shukuri ,  Kenichi Kuroda

    IPC分类号： H01L218242

    CPC分类号： H01L27/10885 ,  H01L27/10814 ,  H01L27/10894

    摘要： In a DRAM having information storage capacitative elements over their corresponding bit lines BL, wiring grooves are defined in an insulating film for wire or interconnection formation, which are formed over a gage electrode serving as word lines of the DRAM. Sidewall spacers are formed on their corresponding side walls of the wiring grooves. Each bit line BL and a first layer interconnection composed of a tungsten film are formed so as to be embedded in the wiring grooves whose intervals are respectively narrowed by the sidewall spacers. The bit lines BL are respectively connected to a semiconductor substrate through connecting plugs. The bit lines BL and the connecting plugs are respectively connected to one another at the bottoms of the wiring grooves.

    摘要翻译： 在具有在其对应位线BL上具有信息存储电容性元件的DRAM中，布线槽被限定在用作线或互连形成的绝缘膜中，其形成在用作DRAM的字线的计量电极上。 侧壁间隔件形成在其相应的布线槽侧壁上。 每个位线BL和由钨膜构成的第一层互连形成为嵌入在间隔被侧壁间隔物分别变窄的布线槽中。 位线BL分别通过连接插头连接到半导体衬底。 位线BL和连接插头在布线槽的底部分别彼此连接。

    Semiconductor integrated circuit device and method for manufacturing the same
    23.
    发明授权
    Semiconductor integrated circuit device and method for manufacturing the same 有权
    半导体集成电路器件及其制造方法

    公开(公告)号：US06503794B1

    公开(公告)日：2003-01-07

    申请号：US09381345

    申请日：1999-09-20

    申请人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

    发明人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

    IPC分类号： H01L218242

    CPC分类号： H01L27/10852 ,  H01L27/105 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10894 ,  Y10S257/90

    摘要： It is an object of the present invention to provide a technology of a semiconductor integrated circuitry that allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operated faster. In a method for manufacturing such a semiconductor integrated circuitry of the present invention, at first, gate electrodes 7 are formed via a gate insulating film 6 on the main surface of a semiconductor substrate 1, and on side surfaces of each of the gate electrodes is formed the first side wall spacer 14 composed of silicon nitride and the second side wall spacer 15 composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area are opened connecting holes 19 and 21 in a self-matching manner with respect to the first side wall spacers 14 and are formed connecting portion connecting a conductor 20 to a bit line BL. In addition, in the N channel MISFETs Qn1 and Qn2, and in the P channel MISFET Qp1 in areas other than the DRAM memory cell area are formed high density N-type semiconductor areas 16 and 16b, as well as a high density P-type semiconductor area 17 in a self-matching manner with respect to the second side wall spacers 15.

    摘要翻译： 本发明的一个目的是提供一种半导体集成电路的技术，该技术允许每个DRAM存储器单元被细分，以便更高集成度和更快地运行。 在本发明的这种半导体集成电路的制造方法中，首先，通过半导体基板1的主面上的栅极绝缘膜6形成栅电极7，在各栅极电极的侧面 形成由氮化硅构成的第一侧壁隔离物14和由氧化硅构成的第二侧壁隔离物15。 然后，在DRAM存储单元区域中的选择MISFET Qs中，以相对于第一侧壁隔板14的自匹配方式打开连接孔19和21，并且形成将导体20连接到位线BL的连接部分。 此外，在N沟道MISFET Qn1和Qn2中以及在DRAM存储单元区域以外的区域中的P沟道MISFET Qp1中形成高密度N型半导体区域16和16b，以及高密度P型 半导体区域17相对于第二侧壁间隔件15以自匹配的方式。

    Method of making semiconductor device with memory cells and peripheral transistors
    25.
    发明授权
    Method of making semiconductor device with memory cells and peripheral transistors 失效
    制造具有存储单元和外围晶体管的半导体器件的方法

    公开(公告)号：US5352620A

    公开(公告)日：1994-10-04

    申请号：US71343

    申请日：1993-06-02

    申请人： Kazuhiro Komori ,  Kenichi Kuroda ,  June Sugiura

    发明人： Kazuhiro Komori ,  Kenichi Kuroda ,  June Sugiura

    IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L27/105 ,  H01L21/70

    CPC分类号： H01L27/11526 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/11546

    摘要： Disclosed is a semiconductor integrated circuit device which includes first field effect transistors of an LDD structure having a floating gate as memory cells and second field effect transistors of the LDD structure as elements other than the memory cells, and which is used as EPROM. A shallow, low impurity concentration region of the first field effect transistor as a part of its source or drain region has a higher impurity concentration than a shallow, low impurity concentration region of the second field effect transistor as a part of its source or drain region.

    摘要翻译： 公开了一种半导体集成电路器件，其包括作为存储单元的浮动栅极的LDD结构的第一场效应晶体管和LDD结构的第二场效应晶体管作为除了存储单元之外的元件，并且被用作EPROM。 作为其源极或漏极区域的一部分的第一场效应晶体管的浅的低杂质浓度区域具有比作为其源极或漏极区域的一部分的第二场效应晶体管的浅的，低杂质浓度区域的杂质浓度更高的杂质浓度 。

    Method of making a semiconductor device having DRAM cells and floating gate memory cells
    26.
    发明授权
    Method of making a semiconductor device having DRAM cells and floating gate memory cells 失效
    制造具有DRAM单元和浮动栅极存储单元的半导体器件的方法

    公开(公告)号：US5057448A

    公开(公告)日：1991-10-15

    申请号：US308700

    申请日：1989-02-10

    申请人： Kenichi Kuroda

    发明人： Kenichi Kuroda

    IPC分类号： H01L21/8239 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/108

    CPC分类号： H01L27/10852 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10805 ,  Y10S438/981

    摘要： In a semiconductor integrated circuit device having a dynamic type memory element (DRAM), a non-volatile memory element of FLOTOX structure and a MISFET, a dielectric film of an information storing capacitance element fo the DRAM and a tunnel insulation film of the non-volatile memory element are constituted in film thickness less than that of a gate insulation film of the MISFET. Thin dielectric film increases the charge storage quantity of the information storing capacitance element and decreases the occupation area of the DRAM. Thin tunnel insulation film increases the tunnel current quantity and decreases the information write time of the non-volatile memory element. Process of forming the dielectirc film and process of forming the tunnel insulation film are performed in the same process, thereby the manufacaturing process of the semiconductor integrated circuit device is reduced.

    摘要翻译： 在具有动态型存储元件（DRAM），FLOTOX结构的非易失性存储元件和MISFET的半导体集成电路器件中，DRAM存储电容元件的电介质膜和非易失性存储元件的隧道绝缘膜， 易失性存储元件的膜厚小于MISFET的栅极绝缘膜的膜厚。 薄电介质膜增加信息存储电容元件的电荷存储量并减小DRAM的占用面积。 薄隧道绝缘膜增加了隧道电流量，降低了非易失性存储元件的信息写入时间。 在相同的工艺中进行形成绝缘膜的工艺和形成隧道绝缘膜的工艺，从而降低了半导体集成电路器件的制造工艺。

    Semiconductor device of an LDD structure having a floating gate
    27.
    发明授权
    Semiconductor device of an LDD structure having a floating gate 失效
    具有浮动栅极的LDD结构的半导体器件

    公开(公告)号：US4663645A

    公开(公告)日：1987-05-05

    申请号：US736770

    申请日：1985-05-22

    申请人： Kazuhiro Komori ,  Kenichi Kuroda ,  June Sugiura

    发明人： Kazuhiro Komori ,  Kenichi Kuroda ,  June Sugiura

    IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/78 ,  H01L29/68

    CPC分类号： H01L27/11526 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/11546 ,  Y10S257/90

    摘要： A semiconductor integrated circuit device is provided which includes first field effect transistors of an LDD structure having a floating gate as memory cells and second field effect transistors of the LDD structure as elements other than the memory cells. A shallow, low impurity concentration region of the first field effect transistor which is a part of its source or drain region has a higher impurity concentration than a shallow, low impurity concentration region of the second field effect transistor which is a part of its source or drain region. The device is particularly useful in an EPROM arrangement.

    摘要翻译： 提供一种半导体集成电路器件，其包括作为存储单元的浮动栅极的LDD结构的第一场效应晶体管和作为存储单元之外的元件的LDD结构的第二场效应晶体管。 作为其源极或漏极区域的一部分的第一场效应晶体管的浅的低杂质浓度区域具有比作为其源极的一部分的第二场效应晶体管的浅的低杂质浓度区域更高的杂质浓度，或 漏区。 该装置在EPROM装置中特别有用。

    Semiconductor device and a method of manufacturing the same and designing the same
    29.
    发明授权
    Semiconductor device and a method of manufacturing the same and designing the same 有权
    半导体装置及其制造方法及其设计方法

    公开(公告)号：US07687914B2

    公开(公告)日：2010-03-30

    申请号：US11978686

    申请日：2007-10-30

    申请人： Kenichi Kuroda ,  Kozo Watanabe ,  Hirohiko Yamamoto

    发明人： Kenichi Kuroda ,  Kozo Watanabe ,  Hirohiko Yamamoto

    IPC分类号： H01L23/48

    CPC分类号： H01L23/5283 ,  H01L21/31053 ,  H01L21/74 ,  H01L21/76224 ,  H01L21/76229 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53228 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/4925 ,  H01L2924/0002 ,  H01L2924/00

    摘要： There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.

    摘要翻译： 提供了一种用于改善嵌入在多个凹部中的构件的表面处的平坦度而不导致制造过程所需时间增加的技术。 根据该技术，通过将相对较宽区域的第一伪图案DP1和相对较小面积的第二虚设图案DP2放置在元件形成区域DA和虚拟区域FA之间的边界BL附近的虚拟图案， 在虚拟区域FA中。 由此，可以在虚拟区域FA的整个部分改善嵌入在隔离槽内的氧化硅膜的表面的平坦度。 此外，当第一伪图案DP1占据虚拟区域FA中相对较宽的区域时，可以控制掩模数据的增加。