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93 条记录 (耗时 0.024 秒)

    Semiconductor integrated circuit
    21.
    发明授权
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US06404056B1

    公开(公告)日：2002-06-11

    申请号：US09313249

    申请日：1999-05-18

    申请人： Shigehiro Kuge ,  Kazutami Arimoto ,  Masaki Tsukude ,  Kazuyasu Fujishima

    发明人： Shigehiro Kuge ,  Kazutami Arimoto ,  Masaki Tsukude ,  Kazuyasu Fujishima

    IPC分类号： H01L2940

    CPC分类号： H01L23/5286 ,  H01L27/0207 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： On transistors P1, P2, N1 and N2 constituting an NAND gate, a interconnection pattern W of metal having high melting point and aluminum interconnection patterns Al1 and Al2 are stacked. A local line LL for connecting transistors P1, P2, N1 and N2 to each other is formed by the interconnection pattern W of metal having high melting point, signal lines SL and SL′ for signal input/output between the NAND gate and the outside are formed by aluminum interconnection pattern Al1, and power supply lines VL and VL′ for applying power supply potentials Vcc and Vss to the NAND gate are formed by the aluminum interconnection pattern Al2. As compared with the prior art in which the local line LL is formed by the aluminum interconnection pattern Al1, the degree of freedom in layout can be improved and the layout area can be reduced.

    摘要翻译： 在构成NAND门的晶体管P1，P2，N1，N2上，堆叠具有高熔点金属的互连图案W和铝互连图案Al1和Al2。 用于将晶体管P1，P2，N1和N2相互连接的本地线路LL通过具有高熔点金属的互连图案W，在与非门与外部之间的信号输入/输出的信号线SL和SL'形成 由铝互连图案Al1形成，并且用于将电源电位Vcc和Vss施加到NAND门的电源线VL和VL'由铝互连图案Al2形成。 与通过铝互连图案Al1形成局部线LL的现有技术相比，可以提高布局的自由度，并且可以减小布局面积。

    Method of manufacturing semiconductor device
    26.
    发明授权
    Method of manufacturing semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US06214664B1

    公开(公告)日：2001-04-10

    申请号：US09443016

    申请日：1999-11-18

    申请人： Hiroshi Kimura ,  Tadashi Nishimura ,  Takahiro Tsuruda ,  Kazutami Arimoto ,  Tadato Yamagata ,  Kazuyasu Fujishima

    发明人： Hiroshi Kimura ,  Tadashi Nishimura ,  Takahiro Tsuruda ,  Kazutami Arimoto ,  Tadato Yamagata ,  Kazuyasu Fujishima

    IPC分类号： H01L218242

    CPC分类号： H01L27/10852

    摘要： In a semiconductor device and a method of manufacturing the same, an isolating and insulating film is provided at an end neighboring to a second impurity region with a groove extended to a semiconductor substrate. This removes a crystal defect existed at the end of the isolating and insulating film, and thus prevents leak of a current at this portion from a storage node. Consequently, provision of the groove at the edge portion of the isolating oxide film neighboring to the impurity region removes a crystal defect at this region, and thus eliminates a possibility of leak of a current.

    摘要翻译： 在半导体器件及其制造方法中，隔离绝缘膜设置在与第二杂质区相邻的端部处，并且沟槽延伸到半导体衬底。 这消除了隔离和绝缘膜末端存在的晶体缺陷，从而防止在该部分处的电流从存储节点泄漏。 因此，在与杂质区相邻的隔离氧化膜的边缘部分处设置沟槽消除了该区域的晶体缺陷，从而消除了电流泄漏的可能性。

    Hierarchical bit line arrangement in a semiconductor memory
    27.
    发明授权
    Hierarchical bit line arrangement in a semiconductor memory 失效
    半导体存储器件中的分层位线布置

    公开(公告)号：US5682343A

    公开(公告)日：1997-10-28

    申请号：US664886

    申请日：1996-06-17

    申请人： Shigeki Tomishima ,  Masaki Tsukude ,  Mikio Asakura ,  Kazuyasu Fujishima

    发明人： Shigeki Tomishima ,  Masaki Tsukude ,  Mikio Asakura ,  Kazuyasu Fujishima

    IPC分类号： G11C11/401 ,  G11C7/18 ,  G11C11/4096 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C5/06

    CPC分类号： G11C7/18 ,  G11C11/4096

    摘要： Main bit lines MBL and ZMBL are disposed at opposite sides of a sense amplifier SA. Main bit lines MBL and ZMBL each are provided for paired sub-bit lines SBL1 and SBL2 (or SBL3 and SBL4). Sub-bit line pair SBL1 and SBL2 is connected to main bit line MBL via a block select switch T1. Sub-bit line pair SBL3 and SBL4 is connected to main bit line ZMBL via a block select switch T2. Since one main bit line is provided for two sub-bit lines, a pitch of the main bit lines is twice as large as a pitch of the sub-bit lines, so that conditions on the pitch of main bit lines are remarkably eased, which facilitates layout of elements.

    摘要翻译： 主位线MBL和ZMBL设置在读出放大器SA的相对侧。 为配对的子位线SBL1和SBL2（或SBL3和SBL4）提供主位线MBL和ZMBL。 子位线对SBL1和SBL2经由块选择开关T1连接到主位线MBL。 子位线对SBL3和SBL4通过块选择开关T2连接到主位线ZMBL。 由于为两个子位线提供一个主位线，所以主位线的间距是子位线的间距的两倍，使得主位线的间距条件显着地减轻，其中 促进元素布局。

    Semiconductor memory device for simple cache system
    28.
    发明授权
    Semiconductor memory device for simple cache system 失效

    公开(公告)号：US5588130A

    公开(公告)日：1996-12-24

    申请号：US283367

    申请日：1994-08-01

    申请人： Kazuyasu Fujishima ,  Yoshio Matsuda ,  Mikio Asakura

    发明人： Kazuyasu Fujishima ,  Yoshio Matsuda ,  Mikio Asakura

    IPC分类号： G06F12/08 ,  G11C7/10 ,  G06F13/00 ,  G11C15/00

    CPC分类号： G06F12/0893 ,  G11C7/1021

    摘要： A semiconductor memory device comprises a DRAM memory cell array comprising a plurality of dynamic type memory cells arranged in a plurality of rows and columns, and an SRAM memory cell array comprising static type memory cells arranged in a plurality of rows and columns. The DRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns. The SRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns, corresponding to the plurality of blocks in the DRAM memory cell array. The SRAM memory cell array is used as a cache memory. At the time of cache hit, data is accessed to the SRAM memory cell array. At the time of cache miss, data is accessed to the DRAM memory cell array. On this occasion, data corresponding to one row in each of the blocks in the DRAM memory cell array is transferred to one row in the corresponding block in the SRAM memory cell array.

    Method and apparatus for driving word line in block access memory
    29.
    发明授权
    Method and apparatus for driving word line in block access memory 失效
    用于在块存取存储器中驱动字线的方法和装置

    公开(公告)号：US5371714A

    公开(公告)日：1994-12-06

    申请号：US26225

    申请日：1993-02-26

    申请人： Yoshio Matsuda ,  Kazuyasu Fujishima ,  Hideto Hidaka

    发明人： Yoshio Matsuda ,  Kazuyasu Fujishima ,  Hideto Hidaka

    IPC分类号： G11C7/10 ,  G11C8/14 ,  G11C8/18 ,  G11C8/00

    CPC分类号： G11C8/14 ,  G11C7/1036 ,  G11C7/1039 ,  G11C8/18 ,  H01L2924/01074

    摘要： In a block access memory in which the memory cell array is divided into a plurality of blocks and data input/output is carried out by block unit, each block is divided into a plurality of subblocks, and the timing of activating the word line and the timing of activating the sense amplifier are made different for each subblock in the block in which the selected word line is included, whereby the peak current associated with the bit line charge/discharge at the time of activating the sense amplifiers is reduced.

    摘要翻译： 在其中存储单元阵列被划分成多个块并且通过块单元执行数据输入/输出的块存取存储器中，每个块被划分成多个子块，并且激活字线和 激活读出放大器的定时对于其中包括所选择的字线的块中的每个子块而言是不同的，从而降低与激活读出放大器时的位线充电/放电相关联的峰值电流。