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28 条记录 (耗时 0.028 秒)

    Space transforming land grid array interposers
    22.
    发明授权
    Space transforming land grid array interposers 有权
    空间变换土地格栅阵列插值

    公开(公告)号：US07473102B2

    公开(公告)日：2009-01-06

    申请号：US11395355

    申请日：2006-03-31

    申请人： Evan George Colgan ,  Paul W. Coteus ,  Hubert Harrer ,  Gareth Geoffrey Hougham ,  John Harold Magerlein ,  John Torok

    发明人： Evan George Colgan ,  Paul W. Coteus ,  Hubert Harrer ,  Gareth Geoffrey Hougham ,  John Harold Magerlein ,  John Torok

    IPC分类号： H01R12/00

    CPC分类号： H05K1/141 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/09701 ,  H01L2924/3011 ,  H01R12/7082 ,  H01R13/2414 ,  H05K2201/0367 ,  H05K2201/049 ,  H05K2201/10378 ,  H05K2201/10719

    摘要： An electronic apparatus includes first and second level package structures and an LGA (land grid array) interposer. The first level package structure includes a package substrate, one or more integrated circuit chips mounted on a first surface of the package substrate, and a first pattern of I/O contacts with pitch P1 formed on a second surface of the package substrate opposite the first surface. The second level package structure includes a second pattern of I/O contacts with pitch P2, wherein P2 is not equal to P1. The LGA interposer is disposed between the first and second level package structures and provides space transform electrical interconnections between the first second patterns of I/O contacts, and further includes a dummy contact formed on at least a first or second surface of the LGA interposer and aligned to an LGA contact on an opposing surface of the LGA interposer.

    摘要翻译： 电子设备包括第一和第二级封装结构以及LGA（焊盘格阵列）插入器。 第一级封装结构包括封装衬底，安装在封装衬底的第一表面上的一个或多个集成电路芯片，以及形成在封装衬底的第二表面上的第一图案的I / O触点，其间距P1与第一 表面。 第二级封装结构包括具有间距P2的I / O触点的第二模式，其中P2不等于P1。 LGA插入器设置在第一和第二级封装结构之间并且在I / O触点的第一第二图案之间提供空间变换电互连，并且还包括形成在LGA插入件的至少第一或第二表面上的虚拟触点和 与LGA插入器的相对表面上的LGA接触对准。

    Chip cooling
    27.
    发明授权
    Chip cooling 有权
    芯片冷却

    公开(公告)号：US06774482B2

    公开(公告)日：2004-08-10

    申请号：US10330742

    申请日：2002-12-27

    申请人： Evan George Colgan ,  John Harold Magerlein ,  Robert Luke Wisnieff ,  Jeffrey Allen Zitz

    发明人： Evan George Colgan ,  John Harold Magerlein ,  Robert Luke Wisnieff ,  Jeffrey Allen Zitz

    IPC分类号： H01L2334

    CPC分类号： H01L23/367 ,  H01L23/42 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/00 ,  H01L2224/0401

    摘要： In an integrated circuit structure, such as in an MCM or in an SCM, a particulate thermally conductive conformable material, such as a thermal paste, is applied between a heat-generating chip and a cooling plate. Modification of the microstructure of at least one of the two nominally parallel surfaces which are in contact with the material is provided in a discrete pattern of sloped recesses. The largest particles in the material preferentially migrate downward into the recesses. The average thickness of the conductive paste is reduced to below the diameter of the largest particles dispersed in the material, providing improved cooling.

    摘要翻译： 在集成电路结构中，例如在MCM或SCM中，在发热芯片和冷却板之间施加诸如导热膏的颗粒状的导热性良好的材料。 改变与材料接触的两个标称平行表面中的至少一个的微观结构以倾斜凹槽的离散图案提供。 材料中最大的颗粒优先向下迁移到凹槽中。 导电膏的平均厚度降低到分散在材料中的最大颗粒的直径以下，提供改进的冷却。

    System of a package fabricated on a semiconductor or dielectric wafer with wiring on one face, vias extending through the wafer, and external connections on the opposing face
    28.
    发明授权
    System of a package fabricated on a semiconductor or dielectric wafer with wiring on one face, vias extending through the wafer, and external connections on the opposing face 有权
    在半导体或电介质晶片上制造的封装的系统，其一面上具有布线，延伸穿过晶片的通孔以及相对面上的外部连接

    公开(公告)号：US06593644B2

    公开(公告)日：2003-07-15

    申请号：US09838725

    申请日：2001-04-19

    申请人： George Liang-Tai Chiu ,  John Harold Magerlein

    发明人： George Liang-Tai Chiu ,  John Harold Magerlein

    IPC分类号： H01L23492

    CPC分类号： H01L23/49827 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/00 ,  H01L2224/0401

    摘要： A semiconductor or dielectric wafer with conducting vias is used as a substrate in an integrated circuit packaging structure, where high density inter and intra chip contacts and wiring are positioned on the substrate face on which the integrated circuitry is mounted, and external signal and power circuitry is contacted through the opposite face. Use of a substrate such as silicon permits the use of conventional silicon processes available in the art for providing high wiring density together with matching of the thermal expansion coefficient of any silicon chips in the integrated circuits. The use of vias through the substrate allows a high density of connections leaving the silicon substrate and provides short paths for the connections of power and signals.

    摘要翻译： 具有导电通孔的半导体或介电晶片用作集成电路封装结构中的基板，其中高密度片间和芯片间接触和布线位于其上安装集成电路的基板面上，以及外部信号和电源电路 通过相对面接触。 使用诸如硅的衬底允许使用本领域可获得的常规硅工艺来提供高布线密度以及集成电路中任何硅芯片的热膨胀系数的匹配。 使用通过基板的通孔允许离开硅衬底的高密度连接并且为功率和信号的连接提供短路径。