公开(公告)号：US07420845B2

公开(公告)日：2008-09-02

申请号：US11701886

申请日：2007-02-02

申请人： Yue-Der Chih

发明人： Yue-Der Chih

IPC分类号： G11C16/06

CPC分类号： G11C16/26

摘要： A memory device includes a set of memory cells, each of which is capable of being selected to generate a sensing current depending on a logic state thereof, and a set of reference cells, each of which is capable of being selected to generate a reference current. A sense amplifier is coupled to the memory cells and the reference cells for comparing the sensing current with the reference current to generate a signal representing the logic state of the selected memory cell. The memory cells and the reference cells are subject to the same operation cycles, such that a difference between the sensing current and the reference current remains a constant.

公开(公告)号：US20070041244A1

公开(公告)日：2007-02-22

申请号：US11204477

申请日：2005-08-16

申请人： Yue-Der Chih ,  Shang-Hsuan Liu

发明人： Yue-Der Chih ,  Shang-Hsuan Liu

IPC分类号： G11C16/04

CPC分类号： G11C16/24 ,  G11C16/12 ,  G11C16/3427

摘要： A method and system is disclosed for prohibiting program disturbance in a memory array device. The system comprises a bit-line decoder coupled to each bit-line of the memory array for providing a predetermined current diverting path, a biased resistance module placed on the bit-line of the flash memory array through which a pull-up current provided by a predetermined power supply is diverted by the bit-line decoder when a cell of the flash memory array connecting to the bit-line is programmed. The programming current of the cell of the flash memory array is stabilized due to the diverted pull-up current.

摘要翻译： 公开了一种用于禁止存储器阵列器件中的程序干扰的方法和系统。 该系统包括耦合到存储器阵列的每个位线的位线解码器，用于提供预定的电流转向路径，位于闪速存储器阵列的位线上的偏置电阻模块，通过该位线线提供上拉电流 当连接到位线的闪速存储器阵列的单元被编程时，位线解码器转移预定的电源。 闪存阵列的单元的编程电流由于转向上拉电流而稳定。

公开(公告)号：US20060176067A1

公开(公告)日：2006-08-10

申请号：US11279918

申请日：2006-04-17

申请人： Yue-Der Chih ,  Ping-Chun Tai

发明人： Yue-Der Chih ,  Ping-Chun Tai

IPC分类号： G01R31/26

CPC分类号： G11C29/025 ,  G11C29/02

摘要： A method and system for detecting a potential reliability problem cause by electrical bridging in an integrated circuit. A voltage difference is created between two conducting lines in the integrated circuit to accelerate the bridging effect for a predetermined period of time. The conducting lines are detected to determine whether an undesired connection has occurred due to the bridging effect between the conducting lines.

摘要翻译： 一种用于检测由集成电路中的电桥引起的潜在可靠性问题的方法和系统。 在集成电路中的两个导线之间产生电压差以加速桥接效应达预定时间段。 检测导线以确定由于导线之间的桥接效应是否发生了不期望的连接。

公开(公告)号：US20050212567A1

公开(公告)日：2005-09-29

申请号：US10808122

申请日：2004-03-24

申请人： Yue-Der Chih ,  Shine Chung

发明人： Yue-Der Chih ,  Shine Chung

IPC分类号： H03B1/00 ,  H03K19/003 ,  H03K19/0175

CPC分类号： H03K19/00315

摘要： A high voltage switch circuit is disclosed for reducing high voltage junction stresses. The circuit contains a cascode device structure having one or more transistors of a same type connected in a series and being operable with a normal operating voltage and a high operating voltage. The cascode device structure comprises a high operating voltage coupled to a first end of the device structure, a low voltage coupled to a second end, and one or more control voltages controllably coupled to the gates of the transistors, wherein at least one of the control voltages coupled to the gate of at least one transistor is raised to a medium voltage level that is higher than a normal operating voltage when operating under the high operating voltage for tolerating stress imposed thereon by the high operating voltage.

摘要翻译： 公开了一种用于降低高压结应力的高压开关电路。 该电路包含具有一个或多个相同类型的晶体管的共源共栅器件结构，其串联连接并可与正常工作电压和高工作电压一起工作。 共射共同体装置结构包括耦合到器件结构的第一端的高工作电压，耦合到第二端的低电压以及可控地耦合到晶体管的栅极的一个或多个控制电压，其中至少一个控制 耦合到至少一个晶体管的栅极的电压在高工作电压下操作时升高到高于正常工作电压的中等电压电平，以容忍由高工作电压施加在其上的应力。

公开(公告)号：US06888754B2

公开(公告)日：2005-05-03

申请号：US10355997

申请日：2003-01-31

申请人： Yue-Der Chih ,  Shu-Chen Chang ,  Hsiao-Hui Chen

发明人： Yue-Der Chih ,  Shu-Chen Chang ,  Hsiao-Hui Chen

IPC分类号： G11C8/00 ,  G11C16/06 ,  G11C16/16

CPC分类号： G11C16/16 ,  G11C16/0425

摘要： This invention provides a memory array and its peripheral circuit with byte-erase capability. The advantage of this invention is the ability to access bytes for program, erase, and read operations. This invention allows this access with the addition of one word line switch and one source line switch for each byte to be accessed for program, erase, and read operations. Also, this invention utilizes a new bias condition to lessen the voltage stress on the high voltage device. In addition, this invention utilizes separate and dedicated power supplies for the local word line driver circuits and for the local source line driver circuits. This is coupled with the partitioning of the main memory array into sub-arrays of 8 columns. This allows the placing of high voltage only on the selected 8 column (byte) subarray. This also substantially lessens the voltage stress on the memory cells and enhances long-term reliability.

摘要翻译： 本发明提供一种具有字节擦除能力的存储器阵列及其外围电路。 本发明的优点是能够访问用于程序，擦除和读取操作的字节。 本发明允许通过添加一个字线开关和一个源线开关来访问用于编程，擦除和读取操作的每个字节的访问。 此外，本发明利用新的偏压条件来减小高压装置上的电压应力。 此外，本发明使用用于本地字线驱动器电路和本地源极线驱动器电路的单独的专用电源。 这与主存储器阵列分割成8列的子阵列相结合。 这允许将高电压放置在所选的8列（字节）子阵列上。 这也大大降低了存储器单元的电压应力并提高了长期的可靠性。

公开(公告)号：US06348832B1

公开(公告)日：2002-02-19

申请号：US09550666

申请日：2000-04-17

申请人： Yue-Der Chih

发明人： Yue-Der Chih

IPC分类号： G05F110

CPC分类号： G05F3/262 ,  G05F3/245

摘要： The current generator circuitry for providing a reference current with small temperature dependence feature is disclosed. The circuitry comprises two PMOS transistors, two NMOS transistors, two diode, as well as two resistors. The first PMOS and NMOS transistors as well as the first diode are in series connected between a power reference and a potential reference. It flows with a primary current. The second PMOS transistor has a gate terminal connected to a gate of the first PMOS transistor thereto connect to a drain terminal of the second PMOS transistor. Furthermore, the second NMOS transistor has a gate terminal connected to a gate of the first NMOS transistor thereof connecting to a drain terminal of the first NMOS transistor. The second PMOS transistor, the second NMOS transistor, the second diode, the first resistor and the second resistor are in series connected between above power reference and the potential reference to flow a reference current. Worth to note, the first resistor has a small temperature coefficient and the second resistor has a large temperature coefficient so that the temperature coefficient of the resistance is close to a critical value, 3.33E-3. As a result the reference current generator has a feature of very small temperature dependence.

摘要翻译： 公开了用于提供具有小的温度依赖特征的参考电流的电流发生器电路。 该电路包括两个PMOS晶体管，两个NMOS晶体管，两个二极管以及两个电阻。 第一个PMOS和NMOS晶体管以及第一个二极管串联在一个功率基准电压和一个电位基准之间。 它与初级电流一起流动。 第二PMOS晶体管具有连接到第一PMOS晶体管的栅极的栅极端子，其连接到第二PMOS晶体管的漏极端子。 此外，第二NMOS晶体管具有连接到其第一NMOS晶体管的栅极的栅极端子，其连接到第一NMOS晶体管的漏极端子。 第二PMOS晶体管，第二NMOS晶体管，第二二极管，第一电阻器和第二电阻器串联连接在上述功率参考和电位参考之间以流过参考电流。 值得注意的是，第一个电阻具有较小的温度系数，第二个电阻具有较大的温度系数，使得电阻的温度系数接近临界值3.33E-3。 因此，参考电流发生器具有非常小的温度依赖性的特征。

公开(公告)号：US09437257B2

公开(公告)日：2016-09-06

申请号：US13765513

申请日：2013-02-12

申请人： Tien-Chun Yang ,  Yue-Der Chih ,  Chan-Hong Chern ,  Tao Wen Chung

发明人： Tien-Chun Yang ,  Yue-Der Chih ,  Chan-Hong Chern ,  Tao Wen Chung

IPC分类号： G11C11/34 ,  G11C7/00 ,  G11C7/02 ,  G11C7/06 ,  G11C7/14 ,  G11C13/00

CPC分类号： G11C7/062 ,  G11C7/14 ,  G11C13/004 ,  G11C2207/063

摘要： A sensing circuit includes a sensing resistor, a reference resistor and a comparator. The comparator has a first input coupled to the sensing resistor, a second input coupled to the reference resistor, and an output. The first input is configured to be coupled to a data bit line associated with a memory cell to receive a sensing input voltage caused by a cell current of the memory cell flowing through the sensing resistor. The second input is configured to be coupled to a reference bit line associated with a reference cell to receive a sensing reference voltage caused by a reference current of the reference cell flowing through the reference resistor. The comparator is configured to generate, at the output, an output signal indicating a logic state of data stored in the memory cell based on a comparison between the sensing input voltage and the sensing reference voltage.

摘要翻译： 感测电路包括感测电阻器，参考电阻器和比较器。 比较器具有耦合到感测电阻器的第一输入端，耦合到参考电阻器的第二输入端和输出端。 第一输入被配置为耦合到与存储器单元相关联的数据位线，以接收由流过感测电阻器的存储单元的单元电流引起的感测输入电压。 第二输入被配置为耦合到与参考单元相关联的参考位线，以接收由参考电池流过参考电阻器的参考电流引起的感测参考电压。 比较器被配置为基于感测输入电压和感测参考电压之间的比较，在输出处产生指示存储在存储器单元中的数据的逻辑状态的输出信号。

公开(公告)号：US08902641B2

公开(公告)日：2014-12-02

申请号：US13443056

申请日：2012-04-10

申请人： Yue-Der Chih ,  Chin-Yi Huang ,  Chun-Jung Lin ,  Kai-Chun Lin ,  Hung-Chang Yu

发明人： Yue-Der Chih ,  Chin-Yi Huang ,  Chun-Jung Lin ,  Kai-Chun Lin ,  Hung-Chang Yu

IPC分类号： G11C11/16 ,  G11C11/15

CPC分类号： G11C11/16 ,  G11C11/15 ,  G11C11/1673

摘要： Magneto-resistive memory bit cells in an array have high or low resistance states storing logic values. During read operations, a bias source is coupled to an addressed memory word, coupling a parameter related to cell resistance to a sense amplifier at each bit position. The sense amplifiers determine whether the parameter value is greater or less than a reference value between the high and low resistance states. The reference value is derived by averaging or splitting a difference of resistances of reference cells at high and/or low resistance states. Bias current is conducted over address lines with varying resistance, due to different distances between the sense amplifiers and addressed memory words, which is canceled by inserting into the comparison circuit a resistance from a dummy addressing array, equal to the resistance of the conductor addressing the selected word line and bit position.

摘要翻译： 阵列中的磁阻存储器位单元具有存储逻辑值的高或低电阻状态。 在读取操作期间，偏置源耦合到寻址的存储器字，将与单元电阻相关的参数耦合到每个位位置的读出放大器。 读出放大器确定参数值是大于还是小于高电阻状态和低电阻状态之间的参考值。 参考值是通过在高和/或低电阻状态下对参考电池的电阻差进行平均或分割得出的。 由于感测放大器和寻址的存储器字之间的距离不同，偏置电流在具有变化的电阻的地址线上进行，这通过将来自虚拟寻址阵列的电阻插入到比较电路中而被抵消，等于导体寻址的电阻 选择的字线和位位置。

公开(公告)号：US08817553B2

公开(公告)日：2014-08-26

申请号：US13052637

申请日：2011-03-21

申请人： Hung-Chang Yu ,  Yue-Der Chih

发明人： Hung-Chang Yu ,  Yue-Der Chih

IPC分类号： G11C7/06 ,  G11C5/14 ,  G11C7/10 ,  G11C8/08

CPC分类号： G11C5/145 ,  G11C5/147 ,  G11C7/12 ,  G11C8/08

摘要： A memory includes a word line having a word line voltage, a charge pump coupled to the word line, and a dynamic feedback control circuit coupled to the charge pump. The dynamic feedback control circuit is capable of changing a clock frequency of a clock signal supplied the charge pump from a first non-zero value to a second non-zero value depending on the difference between the word line voltage and a target threshold voltage.

摘要翻译： 存储器包括具有字线电压的字线，耦合到字线的电荷泵和耦合到电荷泵的动态反馈控制电路。 动态反馈控制电路能够根据字线电压和目标阈值电压之间的差异，将提供给电荷泵的时钟信号的时钟频率从第一非零值改变为第二非零值。

公开(公告)号：US20130286729A1

公开(公告)日：2013-10-31

申请号：US13460487

申请日：2012-04-30

申请人： Yue-Der Chih

发明人： Yue-Der Chih

IPC分类号： G11C11/40

CPC分类号： G11C16/0458 ,  G11C11/5621 ,  H01L29/42348 ,  H01L29/7923

摘要： Non-volatile memory cells and methods. In an apparatus, an array of non-volatile storage cells formed in a portion of a semiconductor substrate includes a first storage cell having a first bit cell and a second bit cell; a second storage cell having a third bit cell and a fourth bit cell; and a column multiplexer coupled to a plurality of column lines, selected ones of the column lines coupled to a first source/drain terminal of the first and the second storage cell and coupled to a second source/drain terminal of the first and second storage cell, the column multiplexer coupling a voltage to one of the column lines connected to the first storage cell corresponding to the data, and coupling a voltage to one of the column lines connected to the second storage cell corresponding to the complementary data. Methods for operating the non-volatile memory cells are disclosed.

摘要翻译： 非易失性存储单元和方法。 在一种装置中，形成在半导体衬底的一部分中的非易失性存储单元的阵列包括具有第一位单元和第二位单元的第一存储单元; 具有第三位单元和第四位单元的第二存储单元; 以及耦合到多条列线的列多路复用器，所述列线中选定的列线耦合到所述第一和第二存储单元的第一源极/漏极端子并且耦合到所述第一和第二存储单元的第二源极/漏极端子 列多路复用器将电压耦合到与数据相对应的连接到第一存储单元的列线之一，并且将电压耦合到与互补数据对应的连接到第二存储单元的列线之一。 公开了用于操作非易失性存储单元的方法。