公开(公告)号：US20070090493A1

公开(公告)日：2007-04-26

申请号：US11248705

申请日：2005-10-11

申请人： Zhong Dong ,  Chiliang Chen ,  Chung Leung

发明人： Zhong Dong ,  Chiliang Chen ,  Chung Leung

IPC分类号： H01L23/58 ,  H01L21/318

CPC分类号： H01L21/3144 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/3145

摘要： Silicon oxide (210) is grown on a silicon region (130). At least a portion (210N) of the silicon oxide (210) adjacent to the silicon region (130) is nitrided. Then some of the silicon oxide (210) is removed, leaving the nitrided portion (210N). Additional silicon oxide is thermally grown on the silicon region (130) under the nitrided silicon oxide portion (210N). This additional silicon oxide and the nitrided portion (210N) form a silicon oxide layer (140) having a high nitrogen concentration adjacent to a surface opposite from the silicon region (130) and a low nitrogen concentration elsewhere. Another nitridation step increases the nitrogen concentration in the silicon oxide layer (140) adjacent to the silicon region, providing a double peak nitrogen profile.

摘要翻译： 氧化硅（210）在硅区（130）上生长。 与硅区域（130）相邻的氧化硅（210）的至少一部分（210 N）被氮化。 然后去除一些氧化硅（210），留下氮化部分（210N）。 另外的氧化硅在氮化硅氧化物部分（210N）下在硅区域（130）上热生长。 该另外的氧化硅和氮化部分（210 N）形成具有与氮区域相反的表面附近的高氮浓度的氧化硅层（140），而在其他地方具有低的氮浓度。 另一个氮化步骤增加邻近硅区域的氧化硅层（140）中的氮浓度，提供双峰氮分布。

公开(公告)号：US06187633B1

公开(公告)日：2001-02-13

申请号：US09169437

申请日：1998-10-09

申请人： Zhong Dong ,  Joe Hui ,  Anqing Zhang

发明人： Zhong Dong ,  Joe Hui ,  Anqing Zhang

IPC分类号： H01L218247

CPC分类号： H01L21/28211 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/511

摘要： The invention is a method of manufacturing a semiconductor memory device using a novel intergate dielectric stack. A key feature of of the invention is the novel O/N/SiON/O structure, forming a silicon oxynitride layer on the silicon nitride layer. The method begins by forming a first insulating layer and a first conductive layer on a semiconductor substrate having one conductivity type. A second insulating layer is formed on the first conducting layer by sequentially stacking: a first silicon oxide layer; a silicon nitride layer; a silicon oxynitride layer; and a second silicon oxide layer. A second conductive layer is formed on the second insulating layer. The first insulating layer, the first conductive layer, the second insulating layer, and the second conductive layer are patterned to form a floating gate, an intergate dielectric, and a control gate. Finally, a source and drain are formed to complete the memory device.

摘要翻译： 本发明是一种制造使用新颖的隔间电介质叠层的半导体存储器件的方法。 本发明的一个关键特征是新型O / N / SiON / O结构，在氮化硅层上形成氧氮化硅层。 该方法开始于在具有一种导电类型的半导体衬底上形成第一绝缘层和第一导电层。 第一绝缘层通过顺序堆叠形成在第一导电层上：第一氧化硅层; 氮化硅层; 氧氮化硅层; 和第二氧化硅层。 在第二绝缘层上形成第二导电层。 将第一绝缘层，第一导电层，第二绝缘层和第二导电层图案化以形成浮栅，隔栅电介质和控制栅极。 最后，形成源极和漏极以完成存储器件。

公开(公告)号：US07807577B2

公开(公告)日：2010-10-05

申请号：US12196067

申请日：2008-08-21

申请人： Zhong Dong ,  Ching-Hwa Chen

发明人： Zhong Dong ,  Ching-Hwa Chen

IPC分类号： H01L21/311

CPC分类号： H01L21/76224 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

摘要： After forming a stack of layers (130, 140, 310) for a transistor or a charge-trapping memory over an active area (110), and before etching isolation trenches (160) in the semiconductor substrate (120) with the stack as a mask, spacers (610) are formed on the stack's sidewalls. The trench etch may include a lateral component, so the top edges of the trenches may be laterally recessed to a position under the spacers or the stack. After the etch, the spacers are removed to facilitate filling the trenches with the dielectric (to eliminate voids at the recessed top edges of the trenches). Other embodiments are also provided.

摘要翻译： 在有源区（110）上形成用于晶体管或电荷俘获存储器的层叠层（130,140,​​310）之后，以及在将堆叠中的隔离沟槽（160）刻蚀为半导体衬底 掩模，间隔物（610）形成在堆叠的侧壁上。 沟槽蚀刻可以包括侧向部件，因此沟槽的顶部边缘可以横向凹入到间隔件或堆叠下的位置。 在蚀刻之后，去除间隔物以便于用电介质填充沟槽（以消除沟槽的凹陷顶部边缘处的空隙）。 还提供了其他实施例。

公开(公告)号：US20090303787A1

公开(公告)日：2009-12-10

申请号：US12134834

申请日：2008-06-06

申请人： Zhong Dong ,  Barbara Haselden

发明人： Zhong Dong ,  Barbara Haselden

IPC分类号： G11C11/34 ,  H01L29/792 ,  H01L21/336

CPC分类号： H01L21/28282 ,  G11C16/0466 ,  H01L29/513 ,  H01L29/792

摘要： In a nonvolatile memory cell with charge trapping dielectric (150), the tunnel dielectric (140) includes chlorine adjacent to the charge trapping dielectric but no chlorine (or less chlorine) adjacent to the cell's channel region (120). The chlorine adjacent to the charge trapping dielectric serves to improve the programming and/or erase speed. The low chlorine concentration adjacent to the channel region prevents chlorine from degrading the data retention. Other features are also provided.

摘要翻译： 在具有电荷捕获电介质（150）的非易失性存储单元中，隧道电介质（140）包括邻近电荷捕获电介质的氯，而与电池的沟道区（120）相邻的氯不含氯（或更少的氯）。 与电荷捕获介质相邻的氯用于改善编程和/或擦除速度。 与通道区相邻的低氯浓度防止氯降解数据保留。 还提供其他功能。

公开(公告)号：US20090039413A1

公开(公告)日：2009-02-12

申请号：US12252571

申请日：2008-10-16

申请人： Zhong Dong ,  Chiliang Chen

发明人： Zhong Dong ,  Chiliang Chen

IPC分类号： H01L29/788

CPC分类号： H01L21/31662 ,  H01L21/02057 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02307 ,  H01L21/02312 ,  H01L29/40114

摘要： Thin oxide films are grown on silicon which has been previously treated with a gaseous or liquid source of chloride ions. The resulting oxide is of more uniform thickness than obtained on untreated silicon, thereby allowing a given charge to be stored on a floating gate formed over said oxide for a longer time than previously required for a structure not so treated.

摘要翻译： 薄氧化膜生长在已经用气态或液态氯离子源处理过的硅上。 所得到的氧化物的厚度比在未处理的硅上获得的厚度更均匀，从而允许将给定的电荷存储在形成于所述氧化物上的浮栅上比未经处理的结构先前需要的时间更长的时间。

公开(公告)号：US07265015B2

公开(公告)日：2007-09-04

申请号：US11174081

申请日：2005-06-30

申请人： Zhong Dong ,  Tai-Peng Lee

发明人： Zhong Dong ,  Tai-Peng Lee

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L29/76

CPC分类号： H01L21/823481 ,  H01L21/28273 ,  H01L21/76224 ,  H01L27/115 ,  H01L27/11521

摘要： Chlorine is incorporated into pad oxide (110) formed on a silicon substrate (120) before the etch of substrate isolation trenches (134). The chlorine enhances the rounding of the top corners (140C) of the trenches when a silicon oxide liner (150.1) is thermally grown on the trench surfaces. A second silicon oxide liner (150.2) incorporating chlorine is deposited by CVD over the first liner (150.1), and then a third liner (150.3) is thermally grown. The chlorine concentration in the second liner (150.2) and the thickness of the three liners (150.1, 150.2, 150.3) are controlled to improve the corner rounding without consuming too much of the active areas (140).

公开(公告)号：US20070138579A1

公开(公告)日：2007-06-21

申请号：US11677768

申请日：2007-02-22

申请人： Zhong Dong ,  Chiliang Chen ,  Chung Leung

发明人： Zhong Dong ,  Chiliang Chen ,  Chung Leung

IPC分类号： H01L29/94

CPC分类号： H01L21/3144 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/3145

摘要： Silicon oxide (210) is grown on a silicon region (130). At least a portion (210N) of the silicon oxide (210) adjacent to the silicon region (130) is nitrided. Then some of the silicon oxide (210) is removed, leaving the nitrided portion (210N). Additional silicon oxide is thermally grown on the silicon region (130) under the nitrided silicon oxide portion (210N). This additional silicon oxide and the nitrided portion (210N) form a silicon oxide layer (140) having a high nitrogen concentration adjacent to a surface opposite from the silicon region (130) and a low nitrogen concentration elsewhere. Another nitridation step increases the nitrogen concentration in the silicon oxide layer (140) adjacent to the silicon region, providing a double peak nitrogen profile.

摘要翻译： 氧化硅（210）在硅区（130）上生长。 与硅区域（130）相邻的氧化硅（210）的至少一部分（210 N）被氮化。 然后去除一些氧化硅（210），留下氮化部分（210N）。 另外的氧化硅在氮化硅氧化物部分（210N）下在硅区域（130）上热生长。 这种附加的氧化硅和氮化部分（210N）形成具有与氮区域相反的表面附近的高氮浓度的氧化硅层（140），而在其它地方具有低的氮浓度。 另一个氮化步骤增加邻近硅区域的氧化硅层（140）中的氮浓度，提供双峰氮分布。

公开(公告)号：US08283733B2

公开(公告)日：2012-10-09

申请号：US12940507

申请日：2010-11-05

申请人： Zhong Dong ,  Ching-Hwa Chen

发明人： Zhong Dong ,  Ching-Hwa Chen

IPC分类号： H01L29/36 ,  H01L29/772

CPC分类号： H01L21/324 ,  H01L21/28167 ,  H01L21/28238 ,  H01L29/78

摘要： Performance of field effect transistors and other channel dependent devices formed on a monocrystalline substrate is improved by carrying out a high temperature anneal in a nitrogen releasing atmosphere while the substrate is coated by a sacrificial oxide coating containing easily diffusible atoms that can form negatively charged ions and can diffuse deep into the substrate. In one embodiment, the easily diffusible atoms comprise at least 5% by atomic concentration of chlorine atoms in the sacrificial oxide coating and the nitrogen releasing atmosphere includes NO. The high temperature anneal is carried out for less than 10 hours at a temperature less than 1100° C.

摘要翻译： 通过在氮气释放气氛中进行高温退火，同时通过包含容易扩散的原子的牺牲氧化物涂层涂覆基底，从而改善在单晶衬底上形成的场效应晶体管和其它通道相关器件的性能，所述牺牲氧化物涂层可形成带负电荷的离子， 可以深层扩散到底物中。 在一个实施方案中，容易扩散的原子在牺牲氧化物涂层中包含至少5％的原子浓度的氯原子，并且氮气释放气氛包括NO。 高温退火在低于1100℃的温度下进行少于10小时。

公开(公告)号：US20110095344A1

公开(公告)日：2011-04-28

申请号：US12940507

申请日：2010-11-05

申请人： Zhong Dong ,  Ching-Hwa Chen

发明人： Zhong Dong ,  Ching-Hwa Chen

IPC分类号： H01L29/772

CPC分类号： H01L21/324 ,  H01L21/28167 ,  H01L21/28238 ,  H01L29/78

摘要： Performance of field effect transistors and other channel dependent devices formed on a monocrystalline substrate is improved by carrying out a high temperature anneal in a nitrogen releasing atmosphere while the substrate is coated by a sacrificial oxide coating containing easily diffusible atoms that can form negatively charged ions and can diffuse deep into the substrate. In one embodiment, the easily diffusible atoms comprise at least 5% by atomic concentration of chlorine atoms in the sacrificial oxide coating and the nitrogen releasing atmosphere includes NO. The high temperature anneal is carried out for less than 10 hours at a temperature less than 1100° C.

摘要翻译： 通过在氮气释放气氛中进行高温退火，同时通过包含容易扩散的原子的牺牲氧化物涂层涂覆基底，从而改善在单晶衬底上形成的场效应晶体管和其它通道相关器件的性能，所述牺牲氧化物涂层可形成带负电荷的离子， 可以深层扩散到底物中。 在一个实施方案中，容易扩散的原子在牺牲氧化物涂层中包含至少5％的原子浓度的氯原子，并且氮气释放气氛包括NO。 高温退火在低于1100℃的温度下进行少于10小时。

公开(公告)号：US20090140318A1

公开(公告)日：2009-06-04

申请号：US11949596

申请日：2007-12-03

申请人： Zhong Dong

发明人： Zhong Dong

IPC分类号： H01L29/68

CPC分类号： H01L29/792 ,  G11C16/0416 ,  H01L29/40117 ,  H01L29/513

摘要： In a nonvolatile memory, the tunnel dielectric (150) has a surface in physical contact with the charge trapping dielectric (160) and also has a surface in physical contact with a semiconductor region providing the active area (120, 130, 140). Under the vacuum level, the bottom edge of the conduction band of the tunnel dielectric (150) is higher at the surface contacting the charge-trapping dielectric (160) than at the surface contacting the active area.

摘要翻译： 在非易失性存储器中，隧道电介质（150）具有与电荷捕获电介质（160）物理接触的表面，并且还具有与提供有源区域（120,130,140）的半导体区域物理接触的表面。 在真空水平下，隧道电介质（150）的导带的底边缘在与电荷捕获电介质（160）接触的表面处比接触有源区的表面高。