公开(公告)号：US20230189444A1

公开(公告)日：2023-06-15

申请号：US17955683

申请日：2022-09-29

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd

Inventor： Xianming CHEN ,  Lei FENG ,  Gao HUANG ,  Benxia HUANG ,  Yejie HONG

IPC: H05K1/18 ,  H05K1/11 ,  H05K1/03 ,  H05K3/00 ,  H05K3/46 ,  H05K3/42

CPC classification number: H05K1/186 ,  H05K1/113 ,  H05K1/0366 ,  H05K3/0035 ,  H05K3/4661 ,  H05K3/429 ,  H05K2201/032 ,  H05K2201/09509 ,  H05K2201/0129 ,  H05K2201/0166 ,  H05K2203/061 ,  H05K2203/308

Abstract: A method for manufacturing a structure for embedding and packaging multiple devices by layer includes preparing a polymer supporting frame, mounting a first device in a first device placement mouth frame to form a first packaging layer, forming a first circuit layer and a second circuit layer, forming a second conductive copper pillar layer and a second sacrificial copper pillar layer, forming a second insulating layer on the first circuit layer, and forming a third insulating layer on the second circuit layer, forming a second device placement mouth frame vertically overlapped with the first device placement mouth frame, mounting a second device and a third device in the second device placement mouth frame to form a second packaging layer, forming a third circuit layer on the second insulating layer. A terminal of the second device and a terminal of the third device are respectively communicated with the third circuit layer.

公开(公告)号：US20230154857A1

公开(公告)日：2023-05-18

申请号：US17957138

申请日：2022-09-30

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd

Inventor： Xianming CHEN ,  Jindong FENG ,  Benxia HUANG ,  Yejie HONG

IPC: H01L23/538 ,  H01L23/373 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/367 ,  H01L25/16

CPC classification number: H01L23/5389 ,  H01L23/3736 ,  H01L24/24 ,  H01L23/5386 ,  H01L23/5383 ,  H01L23/49838 ,  H01L23/49822 ,  H01L21/4882 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3677 ,  H01L25/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/73267 ,  H01L2224/24195

Abstract: A two-sided interconnected embedded chip packaging structure includes a first insulating layer and a second insulating layer. The first insulating layer includes a first conductive copper column layer penetrating through the first insulating layer in a height direction and a first chip located between adjacent first conductive copper columns, and the first chip is attached to the inside of the lower surface of the first insulating layer. The second insulating layer includes a first conductive wire layer and a heat radiation copper surface which are located in the upper surface of the second insulating layer, the first conductive wire layer is provided with a second conductive copper column layer, the first conductive copper column layer is connected with the first conductive wire layer, and the heat radiation copper surface is connected with the reverse side of the first chip.

公开(公告)号：US20220392862A1

公开(公告)日：2022-12-08

申请号：US17663208

申请日：2022-05-12

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd.

Inventor： Xianming CHEN ,  Lei FENG ,  Benxia HUANG ,  Wenshi WANG

IPC: H01L23/00 ,  H01L25/16 ,  H01L23/367 ,  H01L23/49 ,  H01L23/13

Abstract: A package structure with a wettable side surface and a manufacturing method thereof, and a vertical package module are disclosed. The package structure includes a first dielectric layer, a chip and a circuit layer. The first dielectric layer is provided with a package cavity, side wall bonding pads are arranged on a side wall of the first dielectric layer and located outside the package cavity. The chip is packaged inside the package cavity, pins of the chip face first surface of the first dielectric layer. The circuit layer is arranged on the first surface of the first dielectric layer, and the circuit layer is directly or indirectly connected to the side wall bonding pads and the pins of the chip.

公开(公告)号：US20220068825A1

公开(公告)日：2022-03-03

申请号：US17463736

申请日：2021-09-01

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd

Inventor： Xianming CHEN ,  Lei FENG ,  Benxia HUANG ,  Yejie HONG

IPC: H01L23/532 ,  H01L23/538 ,  H01L23/00

Abstract: A connector for implementing multi-faceted interconnection according to an embodiment of the present disclosure includes a first dielectric layer between a first circuit layer and a second circuit layer, a first copper pillar layer connecting the first circuit layer and the second circuit layer in the first dielectric layer, a second dielectric layer on the first circuit layer, a third circuit layer on the second dielectric layer, and a vertical second copper pillar layer connected to the third circuit layer, wherein an opening is formed in the second dielectric layer to expose the first circuit layer, and the second copper pillar layer exposes side faces facing side end faces of the first dielectric layer and the second dielectric layer.

公开(公告)号：US20240178088A1

公开(公告)日：2024-05-30

申请号：US18377379

申请日：2023-10-06

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd

Inventor： Xianming CHEN ,  Gao HUANG ,  Wenjian LIN ,  Juchen HUANG ,  Benxia HUANG

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L23/3121 ,  H01L21/56 ,  H01L23/49822

Abstract: A package substrate includes a first dielectric layer, a first line layer provided on the first dielectric layer, the first line layer including a dam, a second dielectric layer provided on the first dielectric layer and covering the first line layer, a component embedded in the second dielectric layer and surrounded by the dam, and a third dielectric layer provided on the second dielectric layer and covering the component. By providing the dam, it can ensure a good bonding force between dielectric layers by using the dam to effectively avoid an offset problem of the components when the same is embedded in the second dielectric layer as well as omitting a step of baking roughening.

公开(公告)号：US20240113031A1

公开(公告)日：2024-04-04

申请号：US18465889

申请日：2023-09-12

Applicant: Zhuhai ACCESS Semiconductor Co., LTD.

Inventor： Xianming CHEN ,  Lei FENG ,  Qiaoling LI ,  Jun GAO ,  Benxia HUANG ,  Juchen HUANG

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/5383 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49894

Abstract: A semiconductor package structure and a manufacturing method therefor are disclosed. The semiconductor package structure includes a package layer, a first device layer, a first insulation layer, a conductive copper pillar, and a second device layer. The package layer covers the first device layer. The first device layer, the first insulation layer, and the second device layer are sequentially stacked. The conductive copper pillar extends through the first insulation layer. The first device layer and the second device layer are electrically connected through the conductive copper pillar. The first device layer includes a first circuit layer, a trench, and an embedded device. The embedded device is connected to the first circuit layer. The trench is arranged below the embedded device. The trench is partially or completely overlapped with a projection of the embedded device in a mounting direction of the embedded device.

公开(公告)号：US20230369167A1

公开(公告)日：2023-11-16

申请号：US18196012

申请日：2023-05-11

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd

Inventor： Xianming CHEN ,  Juchen HUANG ,  Xiaowei XU ,  Benxia HUANG ,  Gao HUANG

IPC: H01L23/473 ,  H01L23/31 ,  H05K1/02 ,  H05K1/18 ,  H01L23/00

CPC classification number: H01L23/473 ,  H01L23/3121 ,  H01L24/24 ,  H01L24/82 ,  H05K1/0272 ,  H05K1/186 ,  H01L23/49827 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/1003

Abstract: A liquid circulating cooling package substrate includes a circulating cooling structure including a cooling chamber in a first dielectric layer to expose a heat dissipation face, a metal heat dissipation layer on the inner surface of the cooling chamber, an upright support column formed on a metal heat dissipation layer, and a cooling cover supported on the support column to close the cooling chamber along the periphery of the cooling chamber. The metal heat dissipation layer completely covers the heat dissipation face and the inner side surface of the cooling chamber, and a liquid inlet and a liquid outlet are formed on the cooling cover. A circulating cooling structure is provided in the first dielectric layer, and the circulating cooling structure is formed during the processing of an embedded package substrate such that the processing flow is simple and the cost is low.

公开(公告)号：US20230361058A1

公开(公告)日：2023-11-09

申请号：US18175527

申请日：2023-02-27

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd.

Inventor： Xianming CHEN ,  Xiaowei XU ,  Juchen HUANG ,  Benxia HUANG ,  Gao HUANG

IPC: H01L23/64 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/645 ,  H01L23/49822 ,  H01L21/4857

Abstract: A manufacturing method for a substrate embedded with integrated inductor includes: providing a bearing plate; manufacturing a first conduction copper column on the bearing plate; arranging a first dielectric layer on the bearing plate which covers the first conduction copper column; opening the first dielectric layer to form a first opening; filling a magnetic material at the first opening; grinding the first dielectric layer so that surfaces of the first conduction copper column and the magnetic material are flush with a surface of the first dielectric layer; removing the bearing plate, etching a metal layer on the surface of the first dielectric layer to form a package substrate; arranging a first circuit layer and a solder mask layer on an upper surface and a lower surface of the package substrate; and forming a window in the solder mask layer corresponding to the first circuit layer.

公开(公告)号：US20230326765A1

公开(公告)日：2023-10-12

申请号：US18005608

申请日：2021-07-09

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd. ,  NEXPERIA B.V.

Inventor： Xianming CHEN ,  Frank BURMEISTER ,  Lei FENG ,  Yujun ZHAO ,  Benxia HUANG ,  Jinxin YI ,  Jindong FENG ,  Yuan LI ,  Lina JIANG ,  Edward TENA ,  Wenshi WANG

IPC: H01L21/48 ,  H01L21/768 ,  H05K3/34 ,  H05K3/18 ,  H01L23/498

CPC classification number: H01L21/4857 ,  H01L21/4871 ,  H01L21/4828 ,  H01L21/76871 ,  H05K3/3452 ,  H05K3/181 ,  H01L23/49894

Abstract: A package substrate manufacturing method includes: providing a bearing plate, manufacturing a pattern and depositing metal to form the first circuit layer; manufacturing a pattern on the first circuit layer, depositing and etching metal to form a metal cavity, laminating a dielectric layer on the metal cavity, and performing thinning to expose the metal cavity; removing the bearing plate, etching the metal cavity to expose the cavity, depositing metal on the cavity and the dielectric layer, and performing pattern manufacturing and etching to form a second circuit layer; forming a first and second solder mask layers correspondingly on the first and second circuit layers, and performing pattern manufacturing on the first solder mask layer or the second solder mask layer to form a bonding pad; and cutting the cavity, the first circuit layer, the second circuit layer, the first solder mask layer and the second solder mask layer.

公开(公告)号：US20230275023A1

公开(公告)日：2023-08-31

申请号：US18143170

申请日：2023-05-04

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd

Inventor： Xianming CHEN ,  Lei FENG ,  Benxia HUANG ,  Yejie HONG

IPC: H01L23/532 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L23/53228 ,  H01L23/5386 ,  H01L24/14

Abstract: In a method of manufacturing a connector, a first copper pillar layer and a sacrificial copper pillar layer are formed on a temporary bearing plate coated with copper, an etch stop layer is applied on the sacrificial copper pillar layer and electroplated to form a second copper pillar layer, insulating materials is laminated to form a first dielectric layer, a first circuit layer is formed on the first dielectric layer, a second copper pillar layer and a sacrificial copper pillar layer are extended on the first circuit layer, and a sacrificial copper layer is formed on the first circuit layer, insulating material is laminated on the first circuit layer to form a second dielectric layer, the temporary bearing plate is removed, a second and third circuit layers are simultaneously formed on the first and second dielectric layers, and the sacrificial copper layer and the sacrificial copper pillar layer are etched.