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公开(公告)号：US20230081055A1
公开(公告)日：2023-03-16
申请号：US17950708
申请日：2022-09-22
Applicant: pSemi Corporation
Inventor： Poojan Wagh , Kashish Pal
Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.
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公开(公告)号：US11456705B2
公开(公告)日：2022-09-27
申请号：US17074070
申请日：2020-10-19
Applicant: pSemi Corporation
Inventor： Poojan Wagh , Kashish Pal
Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.
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公开(公告)号：US11239801B2
公开(公告)日：2022-02-01
申请号：US15931236
申请日：2020-05-13
Applicant: pSemi Corporation
Inventor： Kashish Pal , Emre Ayranci , Miles Sanner
Abstract: An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a “common source” input transistor, e.g., input field effect transistor (FET), and the second configured in a “common gate” configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration. During split mode, the coupling is added to the circuit to allow some of the signal present at the drain of each input FET to be coupled to the drain of the other input FET.
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公开(公告)号：US11190139B2
公开(公告)日：2021-11-30
申请号：US16882061
申请日：2020-05-22
Applicant: pSemi Corporation
Inventor： Poojan Wagh , Kashish Pal , Robert Mark Englekirk , Tero Tapio Ranta , Keith Bargroff , Simon Edward Willard
Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.
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公开(公告)号：US20210203374A1
公开(公告)日：2021-07-01
申请号：US17141857
申请日：2021-01-05
Applicant: pSemi Corporation
Inventor： Kashish Pal , Vikas Sharma , Sebastian Diebold , Leland Gilreath , Daoud Salameh , Farshid Aryanfar
Abstract: A hybrid coupler-based T/R switch for use in a TDM system. An output hybrid coupler of a balanced amplifier is used to selectively switch a transmit or receive path to an antenna. During transmission, power at the output of the balanced amplifier is delivered directly to the antenna. During reception, power from the antenna is reflected through ports of the hybrid coupler connected to respective two amplifiers of the balanced amplifier, to constructively combine at a port of the coupler coupled to the receive path, with a ninety degrees phase shift. A pair of shunting switches or series switches coupled to the ports of the hybrid coupler connected to the two amplifiers, and a shunting switch coupled to the port coupled to the receive path, control operation of the hybrid coupler-based T/R switch. An additional switch coupled to the port of the coupler that is coupled to the receive path can provide a bypass path for reception or transmission through the antenna while bypassing the balanced amplifier of the transmit path and an amplifier of the receive path.
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Patent Agency Ranking
公开(公告)号：US10700642B2
公开(公告)日：2020-06-30
申请号：US16240601
申请日：2019-01-04
Applicant: pSemi Corporation
Inventor： Poojan Wagh , Kashish Pal , Robert Mark Englekirk , Tero Tapio Ranta , Keith Bargroff , Simon Edward Willard
Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.
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公开(公告)号：US20190190459A1
公开(公告)日：2019-06-20
申请号：US16283298
申请日：2019-02-22
Applicant: pSemi Corporation
Inventor： Poojan Wagh , Kashish Pal
CPC classification number: H03F1/0227 , H03F1/223 , H03F1/301 , H03F1/56 , H03F3/189 , H03F3/193 , H03F2200/18 , H03F2200/249 , H03F2200/453
Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.
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公开(公告)号：US10181819B2
公开(公告)日：2019-01-15
申请号：US15785096
申请日：2017-10-16
Applicant: pSemi Corporation
Inventor： Poojan Wagh , Kashish Pal
Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.
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公开(公告)号：US20240039479A1
公开(公告)日：2024-02-01
申请号：US18447207
申请日：2023-08-09
Applicant: pSemi Corporation
Inventor： Poojan Wagh , Kashish Pal , Robert Mark Englekirk , Tero Tapio Ranta , Keith Bargroff , Simon Edward Willard
CPC classification number: H03F1/0211 , H03F3/193 , H03F1/0261 , H03F1/223 , H03F2200/451 , H03F2200/21 , H03F2200/18 , H03F2200/522
Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.
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30.发明公开公开(公告)号：US20240030897A1
公开(公告)日：2024-01-25
申请号：US18355327
申请日：2023-07-19
Applicant: pSemi Corporation
Inventor： John Birkbeck , Vikas Sharma , Kashish Pal , Mark James O’Leary
CPC classification number: H03H11/20 , H03H11/265 , H03H17/08 , H03H17/0054 , H03H17/0009
Abstract: A phase shifter for altering the phase of a radio frequency signal is disclosed herein. A Lange coupler is used having reflective ports that are coupled to artificial transmission lines. The artificial transmission lines provide a reflection transmission path, the length of which can be determined by digital control lines. Transistors placed along the length of the central trace provide independent paths to ground that serve to shorten the electrical length of the ATL. Accordingly, by selectively turning the transistors on/off, the electrical length of the ATL can be selected and thus the amount of phase delay introduced by the phase shifter.
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