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    Transient Stabilized SOI FETs
    22.
    发明申请
    Transient Stabilized SOI FETs 审中-公开

    公开(公告)号：US20180337146A1

    公开(公告)日：2018-11-22

    申请号：US15600579

    申请日：2017-05-19

    Applicant: pSemi Corporation

    Inventor： Robert Mark Englekirk ,  Keith Bargroff ,  Christopher C. Murphy ,  Tero Tapio Ranta ,  Simon Edward Willard

    IPC: H01L23/60 ,  H01L27/12 ,  H01L29/786 ,  H01L23/66 ,  H01L23/552 ,  H01L29/10 ,  H03K17/687

    Abstract: Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same VDS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same VGS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a “trickle current” state) that keeps both VGS and VDS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.

    Controllable Temperature Coefficient Bias Circuit
    23.
    发明公开
    Controllable Temperature Coefficient Bias Circuit 审中-公开

    公开(公告)号：US20240094757A1

    公开(公告)日：2024-03-21

    申请号：US18359513

    申请日：2023-07-26

    Applicant: pSemi Corporation

    Inventor： Robert Mark Englekirk ,  Keith Bargroff ,  Christopher C. Murphy ,  Tero Tapio Ranta

    IPC: G05F3/26 ,  G05F3/24 ,  H03M1/66

    CPC classification number: G05F3/262 ,  G05F3/242 ,  H03M1/66 ,  H03M1/742

    Abstract: A controllable temperature coefficient bias (CTCB) circuit is disclosed. The CTCB circuit can provide a bias to an amplifier. The CTCB circuit includes a variable with temperature (VWT) circuit having a reference circuit and a control circuit. The control circuit has a control output, a first current control element and a second current control element. Each current control element has a “controllable” resistance. One of the two current control elements may have a relatively high temperature coefficient and another a relatively low temperature coefficient. A controllable resistance of one of the current control elements increases when the controllable resistance of the other current control element decreases. However, the “total resistance” of the current control circuit remains constant with a constant temperature. The VWT circuit has an output with a temperature coefficient that is determined by the relative amount of current that flows through each current control element of the control circuit. A Current Digital to Analog Converter (IDAC) scales the output of the VWT and provides the scaled output to an amplifier bias input.

    Controllable temperature coefficient bias circuit
    25.
    发明授权
    Controllable temperature coefficient bias circuit 有权

    公开(公告)号：US11507125B2

    公开(公告)日：2022-11-22

    申请号：US16989435

    申请日：2020-08-10

    Applicant: pSemi Corporation

    Inventor： Robert Mark Englekirk ,  Keith Bargroff ,  Christopher C. Murphy ,  Tero Tapio Ranta

    IPC: G05F3/26 ,  H03M1/66 ,  G05F3/24 ,  H03M1/74

    Abstract: A controllable temperature coefficient bias (CTCB) circuit is disclosed. The CTCB circuit can provide a bias to an amplifier. The CTCB circuit includes a variable with temperature (VWT) circuit having a reference circuit and a control circuit. The control circuit has a control output, a first current control element and a second current control element. Each current control element has a “controllable” resistance. One of the two current control elements may have a relatively high temperature coefficient and another a relatively low temperature coefficient. A controllable resistance of one of the current control elements increases when the controllable resistance of the other current control element decreases. However, the “total resistance” of the current control circuit remains constant with a constant temperature. The VWT circuit has an output with a temperature coefficient that is determined by the relative amount of current that flows through each current control element of the control circuit. A Current Digital to Analog Converter (IDAC) scales the output of the VWT and provides the scaled output to an amplifier bias input.

    CASCODE AMPLIFIER BIAS CIRCUITS
    26.
    发明申请
    CASCODE AMPLIFIER BIAS CIRCUITS 有权

    公开(公告)号：US20220368287A1

    公开(公告)日：2022-11-17

    申请号：US17843372

    申请日：2022-06-17

    Applicant: pSemi Corporation

    Inventor： Jonathan James Klaren ,  David Kovac ,  Eric S. Shapiro ,  Christopher C. Murphy ,  Robert Mark Englekirk ,  Keith Bargroff ,  Tero Tapio Ranta

    IPC: H03F1/22 ,  H03F3/195 ,  H03F3/213 ,  H03F3/24 ,  H03F1/30 ,  H03F1/56 ,  H03F3/193

    Abstract: Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

    Managed substrate effects for stabilized SOI FETs
    27.
    发明授权
    Managed substrate effects for stabilized SOI FETs 有权

    公开(公告)号：US10971359B2

    公开(公告)日：2021-04-06

    申请号：US16689836

    申请日：2019-11-20

    Applicant: pSemi Corporation

    Inventor： Robert Mark Englekirk ,  Keith Bargroff ,  Christopher C. Murphy ,  Tero Tapio Ranta ,  Simon Edward Willard

    IPC: H01L21/02 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/322 ,  H01L21/265 ,  H01L21/762 ,  H01L27/12 ,  H01L29/786

    Abstract: Modified silicon-on-insulator (SOI) substrates having a trap rich layer, and methods for making such modifications. The modified regions eliminate or manage accumulated charge that would otherwise arise because of the interaction of the underlying trap rich layer and active layer devices undergoing transient changes of state, thereby eliminating or mitigating the effects of such accumulated charge on non-RF integrated circuitry fabricated on such substrates. Embodiments retain the beneficial characteristics of SOI substrates with a trap rich layer for RF circuitry requiring high linearity, such as RF switches, while avoiding the problems of a trap rich layer for circuitry that is sensitive to accumulated charge effects caused by the presence of the trap rich layer, such as non-RF analog circuitry and amplifiers (including power amplifiers and low noise amplifiers).

    Controllable Temperature Coefficient Bias Circuit
    28.
    发明申请
    Controllable Temperature Coefficient Bias Circuit 有权

    公开(公告)号：US20210026391A1

    公开(公告)日：2021-01-28

    申请号：US16989435

    申请日：2020-08-10

    Applicant: pSemi Corporation

    Inventor： Robert Mark Englekirk ,  Keith Bargroff ,  Christopher C. Murphy ,  Tero Tapio Ranta

    IPC: G05F3/26 ,  H03M1/66 ,  G05F3/24

    Abstract: A controllable temperature coefficient bias (CTCB) circuit is disclosed. The CTCB circuit can provide a bias to an amplifier. The CTCB circuit includes a variable with temperature (VWT) circuit having a reference circuit and a control circuit. The control circuit has a control output, a first current control element and a second current control element. Each current control element has a “controllable” resistance. One of the two current control elements may have a relatively high temperature coefficient and another a relatively low temperature coefficient. A controllable resistance of one of the current control elements increases when the controllable resistance of the other current control element decreases. However, the “total resistance” of the current control circuit remains constant with a constant temperature. The VWT circuit has an output with a temperature coefficient that is determined by the relative amount of current that flows through each current control element of the control circuit. A Current Digital to Analog Converter (IDAC) scales the output of the VWT and provides the scaled output to an amplifier bias input.

    Power amplifier self-heating compensation circuit
    30.
    发明授权
    Power amplifier self-heating compensation circuit 有权

    公开(公告)号：US10819290B2

    公开(公告)日：2020-10-27

    申请号：US16253115

    申请日：2019-01-21

    Applicant: pSemi Corporation

    Inventor： Tero Tapio Ranta ,  Keith Bargroff ,  Christopher C. Murphy ,  Robert Mark Englekirk

    IPC: H03F1/30 ,  H03F1/56 ,  H03F3/24 ,  H03F3/195 ,  H03F3/213 ,  H03F3/45 ,  G05F3/26

    Abstract: Temperature compensation circuits and methods for adjusting one or more circuit parameters of a power amplifier (PA) to maintain approximately constant Gain versus time during pulsed operation sufficient to substantially offset self-heating of the PA. Some embodiments compensate for PA Gain “droop” due to self-heating using a Sample and Hold (S&H) circuit. The S&H circuit samples and holds an initial temperature of the PA at commencement of a pulse. Thereafter, the S&H circuit generates a continuous measurement that corresponds to the temperature of the PA during the remainder of the pulse. A Gain Control signal is generated that is a function of the difference between the initial temperature and the operating temperature of the PA as the PA self-heats for the duration of the pulse. The Gain Control signal is applied to one or more adjustable or tunable circuits within a PA to offset the Gain droop of the PA.

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