公开(公告)号：US10313470B2

公开(公告)日：2019-06-04

申请号：US15257026

申请日：2016-09-06

Applicant: Integrated Device Technology, Inc.

Inventor： Mohammad S. Akhter

IPC: H04L29/08 ,  H04L12/24 ,  H04L12/947 ,  H04W4/46 ,  H04W4/44

Abstract: A system includes at least one end-node, at least one edge node, and an edge cloud video headend. The at least one end node generally implements a first stage of a multi-stage hierarchical analytics and caching technique. The at least one edge node generally implements a second stage of the multi-stage hierarchical analytics and caching technique. The edge cloud video headend generally implements a third stage of the multi-stage hierarchical analytics and caching technique.

公开(公告)号：US10261539B2

公开(公告)日：2019-04-16

申请号：US15475328

申请日：2017-03-31

Applicant: Integrated Device Technology, Inc.

Inventor： Jagdeep Bal ,  Ron Wade

IPC: G06F13/38 ,  G06F1/06 ,  G06F1/12 ,  G06F1/08 ,  G06F13/42

Abstract: An apparatus includes a plurality of independently clocked devices and a low frequency beacon. Each of the plurality of independently clocked devices has a respective local clock generator. The low frequency beacon communicates a low frequency synchronization signal to each of the independently clocked devices. The respective local clock generators of the plurality of independently clocked devices are generally synchronized using the low frequency synchronization signal.

公开(公告)号：US10250242B2

公开(公告)日：2019-04-02

申请号：US15089138

申请日：2016-04-01

Applicant: Chengming He

Inventor： Chengming He

IPC: H03K5/133 ,  H03K5/15 ,  H03K3/03 ,  H03K5/1534 ,  H03K21/02 ,  H03K5/131 ,  H03K5/00

Abstract: A signal may be arbitrarily delayed in discrete steps by an arbitrary delay buffer having an analog delay and a digital delay. An analog delay may have a number of selectable delay stages (e.g. ring oscillator with VCDL stages). A digital delay may have rising and falling edge detectors, resettable ring oscillators that oscillate in response to rising or falling edges and counters to count oscillations and generate rising and falling edge delay signals when oscillation counts reach rising and falling edge delay counts. A resettable ring oscillator may have a resettable stage (e.g. VCDL) that may be enabled and disabled. Selection of one or both digital and analog delays and respective delay times may be based on one or more characteristics. For example, an analog delay may delay an input signal or a delayed input signal received from the digital delay based on input signal frequency or total delay.

公开(公告)号：US10200050B1

公开(公告)日：2019-02-05

申请号：US15904320

申请日：2018-02-24

Applicant: Integrated Device Technology, Inc.

Inventor： Chenxiao Ren

IPC: G05F1/00 ,  H02M3/156 ,  H03L7/24 ,  G05F3/04

Abstract: An apparatus including a first circuit and a second circuit. The first circuit may generate an output signal with a regulated voltage and maintain a constant switch frequency having a first on time and a first off time. The second circuit may generate a shifted signal based on a phase delay with respect to the output signal and maintain a shifted frequency having a second on time and a second off time. The second on time may follow the first on time by the phase delay. The second on time may be based on the first on time and transient conditions of a load. The apparatus may implement an automatic phase shift adjustment. A current sensing comparison may implement a cycle-by-cycle comparison between the output signal and the shifted signal to determine the second on time and perform a tuning operation to achieve inductor current balancing.

公开(公告)号：US10199818B2

公开(公告)日：2019-02-05

申请号：US15089413

申请日：2016-04-01

Applicant: INTEGRATED DEVICE TECHNOLOGY, INC.

Inventor： Rosario Pagano ,  Herman R. Paz ,  Siamak Abedinpour

IPC: H02H3/20 ,  H03K17/0412 ,  H03K17/04 ,  H03K17/041 ,  H02J50/10 ,  H02J50/20 ,  H02J50/80

Abstract: A system and method of over-voltage protection includes a switch coupled between a power source and a load, a detection circuit configured to detect an onset of an over-voltage event at the load; and a driver circuit coupled to the switch and the detection circuit. The driver circuit includes a boost sub-circuit that provides a low-resistance path for opening the switch in a boost mode, the boost mode being triggered by the onset of the over-voltage event and having a predetermined duration and a steady state sub-circuit that provides a high-resistance path for holding the switch open during steady state operation when the boost mode.

公开(公告)号：US10075749B2

公开(公告)日：2018-09-11

申请号：US15015568

申请日：2016-02-04

Applicant: Integrated Device Technology, Inc.

Inventor： Haluk Ucar

IPC: H04N21/2389 ,  H04N21/236 ,  H04N21/231 ,  H04N21/2368 ,  H04N21/242 ,  H04N21/2665 ,  H04N21/8547 ,  H04H20/30 ,  H04L29/06 ,  H04N21/2365

CPC classification number: H04N21/23892 ,  H04H20/30 ,  H04L65/4076 ,  H04L65/607 ,  H04N21/23109 ,  H04N21/23605 ,  H04N21/23608 ,  H04N21/23611 ,  H04N21/2365 ,  H04N21/2368 ,  H04N21/242 ,  H04N21/2665 ,  H04N21/8547

Abstract: Examples described include transport stream multiplexers that may not need to search for an appropriate source to use to generate a transport stream packet. Instead, the source to use may be indicated by a position (e.g. an entry) in a memory table, e.g. a metadata array. Methods for placing transport stream packets on a transport stream and initializing the metadata array are also described.

公开(公告)号：US10075284B1

公开(公告)日：2018-09-11

申请号：US15364602

申请日：2016-11-30

Applicant: Integrated Device Technology, Inc.

Inventor： Silvana Rodrigues ,  Michael Rupert ,  Zaher Baidas ,  Leon Goldin

IPC: H04L7/00 ,  H04L7/033 ,  H04L25/49 ,  H04L12/935

CPC classification number: H04L7/033 ,  H04J3/0688 ,  H04J3/0697 ,  H04L25/4902 ,  H04L49/30

Abstract: A system and method for clock phase alignment at a plurality of line cards over a backplane of a communication system. Phase adjustments are continually made for the clock signals at the line cards by dynamically measuring the propagation delay between the timing device and each of the plurality of line cards and continuously communicating the appropriate phase adjustment to each of the plurality of line cards.

公开(公告)号：US20180131412A1

公开(公告)日：2018-05-10

申请号：US15808684

申请日：2017-11-09

Applicant: Integrated Device Technology, Inc.

Inventor： David WILSON ,  Gustavo MEHAS ,  Detelin MARTCHOVSKY

IPC: H04B5/00 ,  H02J50/10

CPC classification number: H04B5/0037 ,  H02J50/10 ,  H02J50/12 ,  H02J50/80 ,  H04B5/0012

Abstract: A wireless power system according to some embodiments includes a wireless power receiver, the wireless power receiver including a receiver coil, a communications device incorporated with the receiver coil, a receiver transceiver coupled to the receiver communications device, and a receiver processor coupled to the receiver transceiver; and a wireless power transmitter, the wireless power transmitter including a transmitter coil, a transmitter communications device incorporated with the transmitter coil, a transmitter transceiver coupled to the transmitter communications device, and a transmitter processor coupled to the transmitter transceiver, wherein communications data is transmitted between the receiver communications device and the transmitter communications device.

公开(公告)号：US09954581B2

公开(公告)日：2018-04-24

申请号：US14168965

申请日：2014-01-30

Applicant: Integrated Device Technology, Inc.

Inventor： Gustavo J. Mehas ,  Vladimir N. Vitchev

IPC: H01F38/00 ,  H04B5/00 ,  H02J7/02 ,  H02J50/12 ,  H02J5/00 ,  H02J17/00 ,  H02M7/219 ,  G05B13/02 ,  H02J50/60

CPC classification number: H04B5/0037 ,  G05B13/0205 ,  H02J5/005 ,  H02J7/025 ,  H02J17/00 ,  H02J50/12 ,  H02J50/60 ,  H02M7/219 ,  H04B5/0031 ,  Y02B70/1441

Abstract: A wireless power enabled apparatus may comprise a wireless power receiver that includes a receive coil configured to generate an AC power signal responsive to a wireless power signal, a rectifier including a plurality of switches configured to receive the AC power signal and generate a DC rectified power signal, a regulator operably coupled with the rectifier to receive the DC rectified power signal and generate an output power signal, and control logic configured to generate a communication signal responsive to adjusting an input impedance of the regulator. A method of operating a wireless power receiver includes generating a rectified voltage responsive to receiving a wireless power signal, generating an output voltage from the rectified voltage with a voltage regulator, and controlling the voltage regulator during a communication mode of wireless power receiver to modulate a characteristic of the voltage regulator with data for transmission to a wireless power transmitter.

公开(公告)号：US20180083487A1

公开(公告)日：2018-03-22

申请号：US15268328

申请日：2016-09-16

Applicant: Integrated Deivce Technology, Inc.

Inventor： Mehmet Nalbant

IPC: H02J50/12 ,  H02J7/02 ,  H02J50/40

Abstract: A multimode receiver can include on or more of an over-voltage protection circuit or a high frequency mode switch. As such, some embodiments of a multi-mode receiver includes a rectifier; a high frequency circuit coupled to the rectifier; a low frequency circuit coupled to the rectifier; and a switching circuit coupled to disable at least a portion of the low frequency circuit while the multi-mode receiver operates in high frequency mode. In some embodiments, the multimode receiver further includes a high-voltage protection circuit coupled to the high frequency circuit that detunes the high frequency circuit when a high-voltage condition is detected.