公开(公告)号：US11842779B2

公开(公告)日：2023-12-12

申请号：US17513612

申请日：2021-10-28

申请人： SK hynix Inc.

发明人： Sung Yong Lim ,  Jae Il Tak

IPC分类号： G11C11/04 ,  G11C16/34 ,  G11C11/56 ,  G11C16/10 ,  G11C16/04

CPC分类号： G11C16/3459 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10

摘要： A memory device includes a memory block, a peripheral circuit, and control logic. The memory block includes memory cells. The peripheral circuit performs a program operation including a plurality of program loops. Each of the plurality of program loops includes a program pulse application operation and a verify operation. The control logic controls the peripheral circuit to store cell status information and apply a program limit voltage. The control logic sets a verify pass reference and applies the program limit voltage determined based on the cell status information.

公开(公告)号：US20230386569A1

公开(公告)日：2023-11-30

申请号：US17825193

申请日：2022-05-26

申请人： SanDisk Technologies LLC

发明人： Xiang Yang ,  Muhammad Masuduzzaman ,  Jiacen Guo

IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C16/10

CPC分类号： G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10

摘要： A method for programming a memory array of a non-volatile memory structure, the memory comprising a population of MLC NAND-type memory cells, wherein the method comprises applying: (1) an inhibit condition to one or more bit lines of the memory array, and (2) a zero voltage condition to one or more bit lines of the memory array such that less than half of the adjacent bit lines of the memory array experience a voltage swing between the inhibit condition and the zero voltage condition.

公开(公告)号：US20230315623A1

公开(公告)日：2023-10-05

申请号：US18206958

申请日：2023-06-07

申请人： Micron Technology, Inc.

发明人： Zhengang Chen ,  Jianmin Huang

IPC分类号： G06F12/02 ,  G06F12/14 ,  G06F13/16 ,  H04L9/06 ,  H04L9/08 ,  G11C11/56

CPC分类号： G06F12/0246 ,  G06F12/1408 ,  G06F13/1668 ,  H04L9/0662 ,  H04L9/0869 ,  G11C11/5628 ,  G06F2212/7207

摘要： Disclosed in some examples are methods, systems, devices, and machine-readable mediums that provide for techniques for scrambling and/or updating meta-data that enable an efficient internal copyback operation. In some examples, improved data distribution techniques decouple the scrambling key from a physical address to allow for copyback operations while maintaining data distribution requirements across a memory device. The controller may generate a seed value that is used by a scrambling algorithm to scramble the host-data and meta-data prior to the data being written. The seed value is then encoded and written to the page with encoded versions of the scrambled user data and meta-data—the random seed is written without scrambling the random seed.

公开(公告)号：US20230290406A1

公开(公告)日：2023-09-14

申请号：US18318417

申请日：2023-05-16

申请人： Kioxia Corporation

发明人： Kosuke YANAGIDAIRA

IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  H01L25/065 ,  G11C16/34

CPC分类号： G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  H01L25/0657 ,  G11C16/3459 ,  H01L2225/06506 ,  H01L2225/06562 ,  H10B41/27

摘要： A semiconductor storage device includes a memory transistor and a word line connected to a gate electrode of the memory transistor. When a write sequence is interrupted before a k+1th verification operation is ended after a kth verification operation is ended in the nth write loop of the write sequence, a voltage equal to or higher than a verification voltage corresponding to a first verification operation in the nth write loop is supplied to the word line before start of the k+1th verification operation after resumption of the write sequence. A time from the resumption of the write sequence to the start of the k+1th verification operation is shorter than a time from start of the first verification operation to end of the kth verification operation in the nth write loop.

公开(公告)号：US11755899B2

公开(公告)日：2023-09-12

申请号：US16751202

申请日：2020-01-23

申请人： Silicon Storage Technology, Inc.

发明人： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC分类号： G11C16/04 ,  G06N3/065 ,  G06F17/16 ,  G11C16/10 ,  G11C16/34 ,  G11C16/26 ,  G11C11/56 ,  G11C16/14 ,  G06N3/044

CPC分类号： G06N3/065 ,  G06F17/16 ,  G06N3/044 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0425 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3459 ,  G11C2216/04

摘要： Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.

公开(公告)号：US11742031B2

公开(公告)日：2023-08-29

申请号：US17554710

申请日：2021-12-17

申请人： KIOXIA CORPORATION

发明人： Masanobu Shirakawa

IPC分类号： G11C16/04 ,  G11C16/26 ,  G11C11/56 ,  G11C7/06 ,  G11C16/34 ,  G11C16/10 ,  H10B43/27 ,  H10B43/35 ,  G11C7/10

CPC分类号： G11C16/26 ,  G11C7/06 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/10 ,  G11C16/3459 ,  H10B43/27 ,  H10B43/35 ,  G11C7/1039 ,  G11C16/0483 ,  G11C2211/562 ,  G11C2211/563 ,  G11C2211/5621 ,  G11C2211/5641 ,  G11C2211/5642

摘要： According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first blocks including a memory cell capable of storing data of one bit, a second block including a memory cell capable of storing data of two or more bits. The semiconductor memory stores first data in a first latch circuit, and second data in a second latch circuit, and writes the first data into one of the first blocks in page units, and the second data into one of the first blocks in page units. The semiconductor memory writes data of at least two pages into the second block, using the first data stored in the first latch circuit and the second data stored in the second latch circuit.

公开(公告)号：US20230253036A1

公开(公告)日：2023-08-10

申请号：US18109390

申请日：2023-02-14

申请人： Mosaid Technologies Incorporated

发明人： HakJune OH ,  Hong Beom PYEON ,  Jin-Ki KIM

IPC分类号： G11C11/56 ,  G11C7/10 ,  G11C16/10 ,  G11C16/26 ,  G06F1/12 ,  G11C16/16 ,  G11C16/34

CPC分类号： G11C11/5628 ,  G06F1/12 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/06

摘要： An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

公开(公告)号：US20230245704A1

公开(公告)日：2023-08-03

申请号：US18095787

申请日：2023-01-11

申请人： Micron Technology, Inc.

发明人： Minjian Wu

IPC分类号： G11C16/14 ,  G11C16/04

CPC分类号： G11C16/14 ,  G11C16/0483 ,  G11C11/5628

摘要： A memory device and method of operation are described. The memory device may include memory cells of a first type that each store a single bit of information and memory cells of a second type that each store multiple bits of information. The memory cells of the first type may be more robust to extreme operating conditions than the second type but may have one or more drawbacks (e.g., lower density). The memory device may identify data to be written, and in response, may identify a temperature of the memory device. If the temperature is within a nominal operating range associated with a low risk of memory errors, the memory device may write the data to the memory cells of the second type. If the temperature is outside the nominal operating range, the memory device may write the data to the memory cells of the first type.

公开(公告)号：US20230245697A1

公开(公告)日：2023-08-03

申请号：US18131511

申请日：2023-04-06

申请人： Kioxia Corporation

发明人： Noboru SHIBATA

IPC分类号： G11C11/56 ,  G11C16/34 ,  G11C16/10

CPC分类号： G11C11/5635 ,  G11C11/5642 ,  G11C16/3459 ,  G11C16/10 ,  G11C11/5628 ,  G11C16/0483

摘要： According to one embodiment, a semiconductor memory device includes a memory cell array, a data storage circuit and a control circuit. The data storage circuit holds first data to be written into the memory cell and holds 1 bit data calculated from the first data. The control circuit writes the data of n bits into the memory cell in a first write operation and then executes a second write operation. The control circuit carries out the following control in the second write operation. It reads data stored in the memory cell in the first write operation. It restores the first data based on the data read from the memory cell and the 1 bit data held in the data storage circuit. It writes the restored first data into the memory cell.

公开(公告)号：US11699485B2

公开(公告)日：2023-07-11

申请号：US17408414

申请日：2021-08-21

申请人： Samsung Electronics Co., Ltd.

发明人： Ho-Sung Ahn ,  Youn-Soo Cheon

IPC分类号： G11C11/56 ,  G11C16/04 ,  G06F3/06 ,  G11C16/14 ,  G11C16/30 ,  G11C16/10

CPC分类号： G11C11/5628 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G11C11/5635 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/30

摘要： Provided herein are a nonvolatile memory device and a method of programming the same. The nonvolatile memory device includes a memory cell array including a plurality of word lines having a first word line and a plurality of memory cells connected to the first word line. The plurality of memory cells includes a plurality of monitoring cells and a plurality of data cells each data cell configured to store N-bit data, N being a natural number. The nonvolatile memory device is configured to perform a first program on the plurality of data cells and a detection program different from the first program on the one or more monitoring cells after performing the first program.