Enhanced turbo product code decoder system
    21.
    发明申请
    Enhanced turbo product code decoder system 失效
    增强型涡轮增压产品代码解码系统

    公开(公告)号:US20040261000A1

    公开(公告)日:2004-12-23

    申请号:US10882576

    申请日:2004-06-30

    摘要: A method and apparatus for decoding a linear block encoded string of information bits comprising: converting the string into a plurality of codewords. Performing hard and soft decisions on each codeword to generate a hard and soft decision vector. Computing the syndrome and finding the location of the two minimum values by Galois Field Arithmetic. Designating these values LOW1 and LOW2 and xoring with a Nc1, thus generating Nc2. Swapping Nc1 with Nc2 and determining the lowest soft decision value, Min1 and a next lowest value, Min2. The two bit locations creating Min1 are designated as MinA and MinB. MinA being replaced with Min2 minus the value MinA. MinB being replaced with Min2 minus the value at MinB. Generating an output codeword by subtracting Min1 from all other bit locations values and 2's complementing all soft values with 0 in their location. Creating the new soft value vector.

    摘要翻译: 一种用于对线性块编码的信息比特串进行解码的方法和装置,包括:将该字符串转换成多个码字。 对每个码字执行硬和软决策,以生成硬和软决策向量。 通过伽罗瓦域算术计算综合征并找出两个最小值的位置。 将这些值指定为LOW1和LOW2,并用Nc1指定,从而生成Nc2。 将Nc1与Nc2交换并确定最低软判决值Min1和下一最低值Min2。 创建Min1的两个位置被指定为MinA和MinB。 MinA被替换为Min2减去MinA值。 MinB被替换为Min2减去MinB的值。 通过从所有其他位位置值中减去Min1来生成输出码字,并且2在其位置上用0互补所有软值。 创建新的软值向量。

    Error-correction multiplexing apparatus, error-correction demultiplexing apparatus, optical transmission system using them, and error-correction multiplexing transmission method
    22.
    发明申请
    Error-correction multiplexing apparatus, error-correction demultiplexing apparatus, optical transmission system using them, and error-correction multiplexing transmission method 失效
    误差校正多路复用装置,纠错解复用装置,使用它们的光传输系统和纠错复用传输方法

    公开(公告)号:US20040170201A1

    公开(公告)日:2004-09-02

    申请号:US10479704

    申请日:2003-12-05

    IPC分类号: H04J003/02

    摘要: A first demultiplexer (11) and a second demultiplexer (12) receive and demultiplex STM-64 data to generate parallel data. A FEC frame generating encoder (13) carries out error correction encoding operation in a column direction of the parallel data that constitutes a matrix, adds a resulting error correcting code to the parallel data, carries out error correction encoding operation in a row direction of the parallel data, and further adds a resulting error-correcting code to the parallel data. A first multiplexer (14) and a second multiplexer (15) multiplex the error-correction-encoded parallel data, and output the data as a FEC frame.

    摘要翻译: 第一解复用器(11)和第二解复用器(12)接收并解复用STM-64数据以产生并行数据。 FEC帧生成编码器(13)在构成矩阵的并行数据的列方向上执行纠错编码操作,将得到的纠错码与并行数据相加,在行方向上执行纠错编码操作 并行数据,并且还将所得到的纠错码添加到并行数据。 第一多路复用器(14)和第二多路复用器(15)对纠错编码的并行数据进行复用,并将数据作为FEC帧输出。

    Code error correcting and detecting apparatus
    23.
    发明授权
    Code error correcting and detecting apparatus 失效
    代码纠错检测装置

    公开(公告)号:US06243845B1

    公开(公告)日:2001-06-05

    申请号:US09098095

    申请日:1998-06-16

    IPC分类号: G11C2900

    摘要: An error correcting and detecting apparatus for a CD-ROM or DVD system executes a high speed decode process. The apparatus includes an input interface, a temporary memory, a correcting circuit, a detecting circuit, a principal memory, and an output interface. The input interface fetches digital data in a block by block manner. The temporary memory stores the fetched digital data in a block by block manner. The correcting circuit performs error correction on digital data read from the temporary memory in a block by block manner using the error correction code and rewrites erroneous digital data to the temporary memory with the corrected digital data. The detecting circuit performs error detection on the error corrected digital data and supplied from the temporary memory in a block by block manner using the error detection code and sets an error flag based on a detection result. The principal memory stores, in a block by block manner, the error corrected digital data supplied to the detecting circuit from the temporary memory. The output interface transfers the error corrected digital data stored in the principal memory to an external unit.

    摘要翻译: 用于CD-ROM或DVD系统的纠错和检测装置执行高速解码处理。 该装置包括输入接口,临时存储器,校正电路,检测电路,主存储器和输出接口。 输入接口以块的方式取出数字数据。 临时存储器以逐块方式存储所读取的数字数据。 校正电路使用纠错码以逐块方式对从临时存储器读取的数字数据执行纠错,并用经校正的数字数据将错误的数字数据重写到临时存储器。 检测电路对误差校正后的数字数据执行错误检测,并使用错误检测码逐块地从临时存储器提供,并根据检测结果设置错误标志。 主存储器以块的方式存储从临时存储器提供给检测电路的纠错数字数据。 输出接口将存储在主存储器中的纠错数字数据传送到外部单元。

    Method and apparatus for performing error correction code operations
    24.
    发明授权
    Method and apparatus for performing error correction code operations 失效
    执行纠错码操作的方法和装置

    公开(公告)号:US6041431A

    公开(公告)日:2000-03-21

    申请号:US933568

    申请日:1997-09-19

    IPC分类号: H03M13/15 H03M13/29 H03M13/00

    摘要: A method for processing encoded data using error control coding in accordance with the present invention includes: a) obtaining Q codewords and P codewords from a storage location, wherein the Q codewords and the P codewords are all obtained in a single pass through the storage location, b) calculating P partial syndromes for said P codewords, c) calculating Q partial syndromes for the Q codewords, and d) storing the Q partial syndromes and the P partial syndromes in a buffer that is separate from the main memory. In some embodiments, storing the Q partial syndromes and the P partial syndromes in the buffer includes storing the Q partial syndromes in a first buffer, and storing the P partial syndromes in a second buffer.

    摘要翻译: 根据本发明的使用错误控制编码处理编码数据的方法包括:a)从存储位置获得Q个码字和P个码字,其中所述Q个码字和P个码字全部通过存储位置 b)计算所述P个码字的P部分校正子,c)计算Q个码字的Q个部分校正子,以及d)将Q个部分校正子和P个部分校正子存储在与主存储器分开的缓冲器中。 在一些实施例中,将Q部分综合征和P部分综合征存储在缓冲器中包括将Q部分综合征存储在第一缓冲器中,并将P部分综合征存储在第二缓冲器中。

    Error correction encoding and decoding system
    26.
    发明授权
    Error correction encoding and decoding system 失效
    纠错编码和解码系统

    公开(公告)号:US5546409A

    公开(公告)日:1996-08-13

    申请号:US378089

    申请日:1995-01-25

    申请人: Katsumi Karasawa

    发明人: Katsumi Karasawa

    IPC分类号: H03M13/29 H03M13/31 H03M13/00

    摘要: In an error correction encoding system, information codes in the form of a data matrix having row addresses and column addresses are stored in memory. A first error correction encoder extracts the stored addresses from the data matrix in the oblique direction and produces a first error-correcting code word from the information codes extracted in the oblique direction. The information codes are extracted in the oblique direction every n row addresses (where n is an integer equal to or greater than 2). A second error correction encoder extracts the information codes from the data matrix in the row direction and produces a second error-correcting code word from the information codes extracted in the row direction.

    摘要翻译: 在纠错编码系统中,具有行地址和列地址的数据矩阵形式的信息代码被存储在存储器中。 第一纠错编码器从倾斜方向的数据矩阵中提取存储的地址,并从倾斜方向提取的信息码产生第一纠错码字。 每n行地址(其中n是等于或大于2的整数)在倾斜方向提取信息码。 第二纠错编码器从行方向上的数据矩阵中提取信息码,并从行方向提取的信息码产生第二纠错码字。

    Method of correcting errors of coded data
    27.
    发明授权
    Method of correcting errors of coded data 失效
    纠正编码数据错误的方法

    公开(公告)号:US5371751A

    公开(公告)日:1994-12-06

    申请号:US718467

    申请日:1991-06-20

    申请人: Yoshiaki Moriyama

    发明人: Yoshiaki Moriyama

    IPC分类号: G06F11/10 H03M13/00 H03M13/29

    摘要: A method of correcting triple-coded data, in which data coded in three different directions is subjected to error correction by referring to first, second and third codes, as well as a first flag determined by the first code and a second flag determined by the second code and other conditions, whereby this method demonstrates high error correcting performance with respect particularly to a burst error.

    摘要翻译: 一种校正三重编码数据的方法,其中通过参考第一,第二和第三代码对三个不同方向编码的数据进行纠错,以及由第一代码确定的第一标志和由 第二代码和其他条件,由此该方法特别涉及突发错误,表现出高纠错性能。

    Staggered parity
    29.
    发明授权

    公开(公告)号:US09831987B2

    公开(公告)日:2017-11-28

    申请号:US15378834

    申请日:2016-12-14

    摘要: Forward Error Correction technique: parity vectors are computed such that each parity vector spans multiple FEC frames; in a given FEC frame, a first set of syndrome bits are due to the parity vectors, and a second set of syndrome bits satisfy FEC equations that involve bits of the given FEC frame including the first set of syndrome bits; and the parity vectors are staggered with respect to any sequence in which the FEC frames are processed. Values of decoded bits of a first frame are deduced from known bits of a first parity vector having an effective length of one frame. For parity vectors having an effective length greater than one frame, a Log Likelihood Ratio of each unknown bit associated with the first frame is updated based on known and unknown bits of each parity vector. First frame is decoded using deduced bit values and updated LLR values.