TIME-BASED DECISION FEEDBACK EQUALIZATION
    21.
    发明申请

    公开(公告)号:US20180351770A1

    公开(公告)日:2018-12-06

    申请号:US15806901

    申请日:2017-11-08

    IPC分类号: H04L25/03 H04L7/00

    摘要: A time-based decision feedback equalizer (TB-DFE) circuit may include a voltage-to-time converter configured to convert a communication signal into a time-based signal. A timing of when an edge of the time-based signal occurs is indicative of a voltage level of the communication signal. The circuit may include a plurality of delay circuits arranged to process the time-based signal in series to generate a delay data signal. The delay circuits may adjust the timing of when the edge of the time-based signal occurs, and a corresponding time delay introduced by each of the delay circuits may be based on a respective weighting factor applied to one or more samples of an output digital signal previously generated by the TB-DFE circuit. A phase detector may compare a timing of an edge of the delay data signal with a reference clock signal and generate the output digital signal based on the comparison.

    Apparatus and methods for tuning a communication link for power conservation
    23.
    发明授权
    Apparatus and methods for tuning a communication link for power conservation 有权
    用于调谐通信链路以进行节能的装置和方法

    公开(公告)号:US09419746B1

    公开(公告)日:2016-08-16

    申请号:US14280351

    申请日:2014-05-16

    IPC分类号: H04L1/00

    摘要: The present disclosure provides apparatus and methods for dynamic analog tuning for power reduction. As disclosed herein, the analog controls on a high-speed serial communication channel are dynamically adjusted in a manner so as to either reduce the total system power or move power dissipation between the transmitter and receiver devices, with little or no negative effect to the bit error rate. One embodiment relates to a method for tuning a communication link. The method includes occasionally determining whether the bit error rate for the communication link is acceptably low. Control parameters for analog circuitry of the communication link are adjusted to decrease power used if the bit error rate is acceptably low and are adjusted to increase power used if the bit error rate is not acceptably low. Other embodiments, aspects and features are also disclosed.

    摘要翻译: 本公开提供了用于功率降低的动态模拟调谐的装置和方法。 如本文所公开的,高速串行通信信道上的模拟控制被动态调整,以便降低总系统功率或者在发射机和接收机设备之间移动功率消耗,对该位很少或没有负面影响 错误率。 一个实施例涉及一种用于调谐通信链路的方法。 该方法包括偶尔地确定通信链路的比特错误率是否可接受地低。 调整通信链路的模拟电路的控制参数,以减少误码率可接受的低功耗,如果误码率不可接受,则调整为增加使用的功率。 还公开了其它实施例,方面和特征。

    METHODS AND APPARATUS FOR CANCELING DISTORTION IN FULL-DUPLEX TRANSCEIVERS
    24.
    发明申请
    METHODS AND APPARATUS FOR CANCELING DISTORTION IN FULL-DUPLEX TRANSCEIVERS 有权
    全双工收发器取消失效的方法和装置

    公开(公告)号:US20100165895A1

    公开(公告)日:2010-07-01

    申请号:US12346591

    申请日:2008-12-30

    IPC分类号: H04B3/20

    摘要: Methods and apparatus for canceling distortion in full-duplex transceivers are disclosed. Some example methods to reduce distortion in a full-duplex transceiver include generating a first digital signal, generating a first analog signal based on the first digital signal for transmission over a full-duplex channel, receiving a second analog signal via the full-duplex channel, and generating a second digital signal based on the second analog signal, wherein the second digital signal includes coupling distortion based on the first analog signal. The example methods further include generating an adaptive filter signal based on the first digital signal, and reducing the coupling distortion from the second digital signal by subtracting the adaptive filter signal from the second digital signal.

    摘要翻译: 公开了用于消除全双工收发器失真的方法和装置。 减少全双工收发器失真的一些示例性方法包括产生第一数字信号,基于第一数字信号产生第一模拟信号以便在全双工信道上传输,经由全双工信道接收第二模拟信号 并且基于所述第二模拟信号产生第二数字信号,其中所述第二数字信号包括基于所述第一模拟信号的耦合失真。 示例性方法还包括基于第一数字信号产生自适应滤波器信号,并且通过从第二数字信号中减去自适应滤波器信号来减少来自第二数字信号的耦合失真。

    SAMPLED CURRENT-INTEGRATING DECISION FEEDBACK EQUALIZER AND METHOD
    25.
    发明申请
    SAMPLED CURRENT-INTEGRATING DECISION FEEDBACK EQUALIZER AND METHOD 有权
    采样电流一体化决策反馈均衡器和方法

    公开(公告)号:US20090252215A1

    公开(公告)日:2009-10-08

    申请号:US12061268

    申请日:2008-04-02

    IPC分类号: H04L27/01

    CPC分类号: H04L25/03019 H04L25/03031

    摘要: A decision feedback equalizer (DFE) and method including a branch coupled to an input and including a sample-and-hold element configured to receive and sample a received input signal from the input and a current-integrating summer. The current-integrating summer is coupled to an output of the sample-and-hold element. The summer is configured to receive and sum currents representing at least one previous decision and an input sample. The at least one previous decision and the input sample are integrated onto a node, wherein the input sample is held constant during an integration period, thereby mitigating the effects of input transitions on an output of the summer.

    摘要翻译: 一种判决反馈均衡器(DFE)和方法,包括耦合到输入端并包括采样保持元件的分支,所述采样保持元件被配置为从所述输入端接收和采样所接收的输入信号以及电流积分夏令。 电流积分加法器与采样保持元件的输出耦合。 夏天被配置为接收并且表示至少一个先前决定和输入样本的和电流。 至少一个先前的决定和输入样本被集成到节点上,其中输入样本在积分期间保持不变,从而减轻输入转换对夏季输出的影响。

    Adaptive demodulating method for generating replica and demodulator
thereof
    26.
    发明授权
    Adaptive demodulating method for generating replica and demodulator thereof 失效
    用于产生其副本和解调器的自适应解调方法

    公开(公告)号:US5602507A

    公开(公告)日:1997-02-11

    申请号:US411748

    申请日:1995-04-03

    申请人: Hiroshi Suzuki

    发明人: Hiroshi Suzuki

    CPC分类号: H04B3/23 H04L25/03031

    摘要: To prevent a coefficient vector for a modulated wave candidate of repeated identical codes from diverging, an error calculating part (36) calculates the difference between a vector X(i) with elements of input signals x(i) at N successive times and a vector Y.sub.m (i) of N replica signals y.sub.m (i) received from a transversal filter (34) to obtain an error vector E.sub.m (i), the square of the norm of which is supplied to a maximum likelihood sequence estimating portion (31), when signal estimation is carried out. In addition, a code sequence candidate {a.sub.m } is produced and a corresponding modulated wave candidate s.sub.m is generated. The filter (34) calculates the inner product of the modulated wave candidate s.sub.m and the coefficient vector W.sub.m (i-1) corresponding to each state to produce y.sub.m (i). W.sub.m (i-1) of each state is updated to W.sub.m (i) using an inner product vector of a generalized inverse matrix produced from s.sub.m corresponding to the state transition selected by the estimating portion (31) and E.sub.m (i).

    摘要翻译: PCT No.PCT / JP94 / 01862 Sec。 371日期:1995年4月3日 102(e)日期1995年4月3日PCT 1994年11月4日PCT PCT。 公开号WO95 / 12926 日期1995年5月11日为了防止来自发散的重复相同代码的调制波候选的系数向量,误差计算部分(36)计算在N个连续的输入信号x(i)的元素之间的向量X(i) 次数和从横向滤波器(34)接收的N个复制信号ym(i)的向量Ym(i),以获得误差向量Em(i),其范数的平方被提供给最大似然序列估计部分 (31),当执行信号估计时。 此外,产生代码序列候选{am},并生成对应的调制波候选sm。 滤波器(34)计算调制波候选sm的内积和与各状态对应的系数矢量Wm(i-1),生成ym(i)。 使用由对应于由估计部分(31)和Em(i)选择的状态转换的sm产生的广义逆矩阵的内积向量,将每个状态的Wm(i-1)更新为Wm(i)。

    Automatic equalizer
    27.
    发明授权
    Automatic equalizer 失效
    自动均衡器

    公开(公告)号:US5422606A

    公开(公告)日:1995-06-06

    申请号:US52392

    申请日:1993-04-23

    申请人: Yoshinori Tanaka

    发明人: Yoshinori Tanaka

    CPC分类号: H04L25/03031

    摘要: An automatic equalizer includes a transversal filter having delay elements with N+1 taps and N+1 multipliers for outputting an output signal Y.sub.n which is described by the following formula (A) depending on a modulated input signal X.sub.n which is received via a transmission path and a coefficient C.sub.i.sup.(n) of each of the multipliers which are arranged in a sequence such that an integer i increases from -(N/2) to (N/2) towards latter stages of the delay elements, ##EQU1## a gain controller for multiplying a gain coefficient g.sup.(n) to the output signal Y.sub.n of the transversal filter to produce an equalizer output, and a control circuit responsive to the equalizer output for variably setting the coefficient C.sub.i.sup.(n) of the transversal filter means described by the following formula (B) and the gain coefficient g.sup.(n) of the gain controller described by the following formula (C)C.sub.i.sup.(n+1) =C.sub.i.sup.(n) +.alpha.E.sub.n.sup.* X.sub.n-i-(N/2)(B)g.sup.(n) =g.sup.(n) +.tau.E.sub.n.sup.* Y.sub.n (C)where i.noteq.0, E.sub.n denotes an error of the output signal Y.sub.n, E.sub.n.sup.* denotes a complex conjugate of the error E.sub.n, and .alpha. and .tau. denote scaler coefficients, so that a frequency distortion dependent on a transmission characteristic of the transmission path is compensated.

    摘要翻译: 自动均衡器包括具有N + 1抽头的延迟元件和N + 1个乘法器的横向滤波器,用于输出根据经由传输路径接收的调制输入信号Xn由下式(A)描述的输出信号Yn 和每个乘法器的系数Ci(n),其按照使得整数i从 - (N / 2)到(N / 2)朝向后级的延迟元件增加的顺序排列,(A )增益控制器,用于将增益系数g(n)与横向滤波器的输出信号Yn相乘以产生均衡器输出;响应于均衡器输出的控制电路,用于可变地设置横向滤波器的系数Ci(n) 由以下公式(C)描述的增益控制器的下列公式(B)和增益系数g(n)描述的装置Ci(n + 1)= Ci(n)+αEn* Xn-i-(N / 2)(B)g(n)= g(n)+ tau En * Yn(C)其中i NOTEQUAL 0,En表示输出信号Yn的误差, En *表示误差En的复共轭,α和τ表示缩放系数,从而补偿依赖于传输路径的传输特性的频率失真。

    Redistribution circuit for analog to digital and digital to analog conversion and multilevel pre-equalizers
    28.
    发明授权
    Redistribution circuit for analog to digital and digital to analog conversion and multilevel pre-equalizers 失效
    用于模拟数字和数字转换为模拟转换和多种前置均衡器的重新分配电路

    公开(公告)号:US3651518A

    公开(公告)日:1972-03-21

    申请号:US3651518D

    申请日:1970-03-11

    IPC分类号: H03M1/00 H04L25/03 H03K13/12

    摘要: Each of a plurality of capacitors is charged to a weighted reference charge or discharged in response to digital information. At a subsequent time, all capacitors are connected in parallel and charge redistributes among them. The redistribution voltage which thereby settles across the parallel combination corresponds to an analog sample voltage.

    摘要翻译: 将多个电容器中的每一个充电到加权参考电荷或响应于数字信息而放电。 在随后的时间,所有电容器并联连接,并在其间重新分配电荷。 由此平行组合的再分配电压对应于模拟采样电压。