公开(公告)号：US20160134394A1

公开(公告)日：2016-05-12

申请号：US14536303

申请日：2014-11-07

Applicant: INPHI CORPORATION

Inventor： Arun TIRUVUR ,  Sudeep BHOJA

IPC: H04L1/00 ,  H04Q11/00

CPC classification number: H04L25/03 ,  H04L1/004 ,  H04L1/0061 ,  H04L5/0048 ,  H04L25/03057 ,  H04L25/03885 ,  H04L25/4917 ,  H04L27/04 ,  H04L27/06 ,  H04L2025/03636 ,  H04Q11/0062 ,  H04Q2011/0088

Abstract: The present invention is directed to data communication systems and methods. More specifically, embodiments of the present invention provide techniques for transceivers to quickly identify FEC mode used in data communication. A transmitting transceiver embeds FEC mode information in a designated field of an alignment marker. The receiving transceiver acknowledges the receipt of the FEC mode information and processes the incoming data accordingly. There are other embodiments as well.

Abstract translation: 本发明涉及数据通信系统和方法。 更具体地，本发明的实施例提供了用于收发机快速识别在数据通信中使用的FEC模式的技术。 发送收发器将FEC模式信息嵌入到对准标记的指定字段中。 接收收发器确认接收到FEC模式信息并相应地处理输入数据。 还有其它实施例。

公开(公告)号：US20160072620A1

公开(公告)日：2016-03-10

申请号：US14872327

申请日：2015-10-01

Applicant: INPHI CORPORATION

Inventor： James L. GORECKI ,  Jiayun ZHANG ,  Marcial K. CHUA ,  Cosmin IORGA

IPC: H04L7/04 ,  H03K5/135

CPC classification number: H04L7/04 ,  H03K5/01 ,  H03K5/135 ,  H03K2005/00052 ,  H03K2005/00286 ,  H03L7/00 ,  H03L7/0807

Abstract: Apparatus to implement several high performance phase interpolators are disclosed. Some embodiments are directed to a full-wave integrating phase interpolation core comprising two pairs of in-phase and quadrature-phase current DACs arranged in a cascode architecture to drive an integrating capacitor and produce an interpolation voltage waveform. The current DACs are biased, weighted, and controlled by in-phase and quadrature-phase input clocks to yield an interpolation waveform that presents a phase value between the phases of the input clocks. Some embodiments deploying the interpolator core use feedback circuitry and reference voltages to adjust the common mode and amplitude of the interpolation voltage waveform to obtain both optimal performance and operation within the interpolator linear region or output compliance range. Both the single-core and dual-core implementations, as well as other implementations of the interpolator core, exhibit high power supply rejection, highly linear interpolation, a wide frequency range, and low cost duty cycle correction.

Abstract translation: 公开了实现若干高性能相位内插器的装置。 一些实施例涉及一种全波积分相位插值核心，其包括以共源共轭结构布置的两对同相和正交相电流DAC，以驱动积分电容器并产生内插电压波形。 当前DAC被偏置，加权并由同相和正交相输入时钟控制，以产生呈现输入时钟的相位之间的相位值的内插波形。 部署内插器核心的一些实施例使用反馈电路和参考电压来调整内插电压波形的共模和幅度，以获得内插器线性区域或输出一致性范围内的最佳性能和操作。 单核和双核实现以及内插器内核的其他实现都表现出高电源抑制，高线性内插，宽频率范围和低成本占空比校正。

公开(公告)号：US09258155B1

公开(公告)日：2016-02-09

申请号：US14597120

申请日：2015-01-14

Applicant: INPHI CORPORATION

Inventor： Jamal Riani ,  Sudeep Bhoja

IPC: H04L25/03

CPC classification number: H04L25/03 ,  H04L1/004 ,  H04L1/0061 ,  H04L5/0048 ,  H04L25/03057 ,  H04L25/03885 ,  H04L25/4917 ,  H04L27/04 ,  H04L27/06 ,  H04L2025/03636 ,  H04Q11/0062 ,  H04Q2011/0088

Abstract: The present invention is directed to data communication systems and methods. More specifically, embodiments of the present invention provide a communication system that removes reflection signals. A digital data stream is processed through both tentative path and the main path. The tentative path uses a first DFE device and a reflection cancellation circuit to generate a correction signal for removing reflection signal from the digital data stream. A second DFE device removes ISI and other noises from the corrected digital data stream. There are other embodiments as well.

Abstract translation: 本发明涉及数据通信系统和方法。 更具体地，本发明的实施例提供一种消除反射信号的通信系统。 通过临时路径和主路径处理数字数据流。 暂定路径使用第一DFE装置和反射消除电路来产生用于从数字数据流中去除反射信号的校正信号。 第二个DFE设备从校正的数字数据流中去除ISI和其他噪声。 还有其它实施例。

公开(公告)号：US09250831B1

公开(公告)日：2016-02-02

申请号：US14194574

申请日：2014-02-28

Applicant: INPHI CORPORATION

Inventor： Nirmal Raj Saxena ,  Sreenivas Krishnan ,  David Wang

IPC: G06F12/10 ,  G06F3/06 ,  G06F13/40 ,  G06F12/08

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0613 ,  G06F3/0635 ,  G06F3/0644 ,  G06F3/0658 ,  G06F3/067 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0813 ,  G06F13/4022 ,  Y02D10/14 ,  Y02D10/151

Abstract: Techniques for a massively parallel and memory centric computing system. The system has a plurality of processing units operably coupled to each other through one or more communication channels. Each of the plurality of processing units has an ISMn interface device. Each of the plurality of ISMn interface devices is coupled to an ISMe endpoint connected to each of the processing units. The system has a plurality of DRAM or Flash memories configured in a disaggregated architecture and one or more switch nodes operably coupling the plurality of DRAM or Flash memories in the disaggregated architecture. The system has a plurality of high speed optical cables configured to communicate at a transmission rate of 100 G or greater to facilitate communication from any one of the plurality of processing units to any one of the plurality of DRAM or Flash memories.

Abstract translation: 大规模并行和以内存为中心的计算系统的技术。 该系统具有通过一个或多个通信信道彼此可操作地耦合的多个处理单元。 多个处理单元中的每一个具有ISMn接口装置。 多个ISMn接口设备中的每一个耦合到连接到每个处理单元的ISMe端点。 该系统具有以分解体系结构配置的多个DRAM或闪存，以及可操作地以分解结构耦合多个DRAM或闪速存储器的一个或多个交换节点。 该系统具有多个高速光缆，其配置为以100G或更大的传输速率进行通信，以便于从多个处理单元中的任何一个到多个DRAM或闪存中的任何一个的通信。

公开(公告)号：US09240248B2

公开(公告)日：2016-01-19

申请号：US14473872

申请日：2014-08-29

Applicant: INPHI CORPORATION

Inventor： Hamid Reza Rategh ,  David T. Wang ,  Lawrence Tse

IPC: G11C11/34 ,  G11C29/04 ,  G11C8/06 ,  G11C5/04 ,  G11C29/44 ,  G11C7/10 ,  G11C11/413 ,  G11C16/08 ,  G11C29/00 ,  G11C29/08

CPC classification number: G11C29/04 ,  G11C5/04 ,  G11C7/1012 ,  G11C8/06 ,  G11C11/413 ,  G11C16/08 ,  G11C29/08 ,  G11C29/44 ,  G11C29/76 ,  G11C29/785 ,  G11C2029/4402

Abstract: An integrated circuit device. The device includes an address input(s) configured to receive address information from an address stream from an address command bus coupled to a host controller and an address output(s) configured to drive address information, and is coupled to a plurality of memory (DRAM) devices provided on a DIMM. The device has an address match table comprising a non-volatile memory device configured to store at least a revised address corresponding to a spare memory location and a bad address of at least one of the plurality of memory (DRAM) devices. The device has a control module configured to process and determine whether each address matches with a stored address in the address match table to identify the bad address and configured to replace the bad address with the revised address of the spare memory location.

Abstract translation: 集成电路器件。 该设备包括被配置为从地址流接收地址信息的地址输入，该地址信息来自耦合到主机控制器的地址命令总线和被配置为驱动地址信息的地址输出，并被耦合到多个存储器 DRAM）设备。 该设备具有包括非易失性存储器设备的地址匹配表，其被配置为至少存储对应于多个存储器（DRAM）设备中的至少一个的备用存储器位置和不良地址的修改地址。 该设备具有控制模块，该控制模块被配置为处理并确定每个地址是否与地址匹配表中存储的地址相匹配，以识别不良地址并将其配置为用备用存储器位置的修改地址替换坏地址。

公开(公告)号：US09185823B2

公开(公告)日：2015-11-10

申请号：US14576008

申请日：2014-12-18

Applicant: INPHI CORPORATION

Inventor： Christopher Haywood ,  Chao Xu ,  Fouad G. Tamer

IPC: G06F3/00 ,  G06F13/00 ,  H05K7/14 ,  G11C8/00 ,  H05K7/20

CPC classification number: G06F13/28 ,  G06F13/4027 ,  G06F13/4282 ,  G11C8/00 ,  H05K7/1487 ,  H05K7/1488 ,  H05K7/1489 ,  H05K7/1491 ,  H05K7/1492 ,  H05K7/20836 ,  Y02D10/14 ,  Y02D10/151

Abstract: The present invention is directed to server systems and methods thereof. More specifically, embodiments of the present invention provides a memory controller within a server system, where the memory controller is disengageably connected to one or more processors, a plurality of volatile memory modules, and plurality of solid-state memory modules. This memory controller may be connected to other similarly configured memory controllers. The volatile and solid-state memory modules can be removed and/or replaced. There are other embodiments as well.

公开(公告)号：US20150309252A1

公开(公告)日：2015-10-29

申请号：US14262621

申请日：2014-04-25

Applicant: INPHI CORPORATION

Inventor： Masaki KATO ,  Radha NAGARAJAN

IPC: G02B6/12 ,  G02B6/10

CPC classification number: G02B6/126 ,  G02B6/105 ,  G02B6/12 ,  G02B6/12009 ,  G02B6/12014 ,  G02B6/12023 ,  G02B6/122 ,  G02B6/124 ,  G02B6/2773 ,  G02B6/2861 ,  G02B6/29325 ,  G02B6/2938 ,  G02B2006/12061 ,  G02B2006/12107 ,  G02B2006/12123 ,  G02B2006/1215

Abstract: A silicon photonics device and system therefor. The silicon photonics device can include a 300 nm SOI (silicon-on-insulator with 300 nm top Si) overlying a substrate member. A waveguide structure can be configured from a portion of the SOI layer and disposed overlying the substrate member. This waveguide structure can include an AWG (Arrayed Waveguide Gratings) structure with 300 nm×300 nm symmetric grating waveguides or an Echelle grating structure characterized by a top silicon thickness of 300 nm. The waveguide structure can also include an index compensator material configured to provide at least two material index ratings in the waveguide structure.

Abstract translation: 一种硅光子器件及其系统。 硅光子器件可以包括覆盖在衬底构件上的300nm SOI（具有300nm顶部Si的绝缘体上硅）。 波导结构可以由SOI层的一部分配置并且设置在衬底构件上。 该波导结构可以包括具有300nm×300nm对称光栅波导的AWG（阵列波导光栅）结构或以300nm的顶部硅厚度为特征的Echelle光栅结构。 波导结构还可以包括配置为在波导结构中提供至少两个材料折射率等级的折射率补偿器材料。

公开(公告)号：US20150280902A1

公开(公告)日：2015-10-01

申请号：US14637308

申请日：2015-03-03

Applicant: INPHI CORPORATION

Inventor： Karthik S. GOPALAKRISHNAN ,  Guojun REN

IPC: H04L7/033 ,  H03L7/081 ,  H04L27/04

CPC classification number: H04L7/0331 ,  H03K5/131 ,  H03K5/135 ,  H03L7/08 ,  H03L7/0814 ,  H04L27/04

Abstract: A phase interpolator (PI) is provided to adjust the phase of a clock such that the phase is aligned to an incoming data pattern from a data stream. The data can be captured from a device such as a flip-flop or the like. The present technique uses a PI (digital to phase) and a digital state machine in a feedback loop to set the correct digital code to the PI inputs to achieve an appropriate clock phase. Of course, there can be variations.

Abstract translation: 提供相位插值器（PI）以调整时钟的相位，使得该相位与来自数据流的输入数据模式对准。 可以从诸如触发器等的装置捕获数据。 本技术在反馈环路中使用PI（数字到相位）和数字状态机将正确的数字代码设置为PI输入以实现适当的时钟相位。 当然可以有变化。

公开(公告)号：US09099165B1

公开(公告)日：2015-08-04

申请号：US13791792

申请日：2013-03-08

Applicant: Inphi Corporation

Inventor： Chien-Hsin Lee

IPC: G11C29/04 ,  G11C8/06 ,  G11C16/08

CPC classification number: G11C8/06 ,  G11C29/848

Abstract: A memory device comprising an interface device and a plurality of memory arrays. The interface device includes an address match table comprising at least a revised address corresponding to a spare memory location and a control module configured to determine address information from the address stream from an address command bus coupled to the host controller during a run time operation. The control module is configured to compare each address from the address stream and determine whether each address matches with a stored address in the address match table to identify a bad address and configured to replace the bad address with the revised address of the spare memory location. The device also has a plurality of memory arrays. Each of the memory arrays comprises a plurality of memory cells. The memory device has a spare group of memory cells comprising a plurality of spare memory cells. Each of the plurality of spare memory cells being addressable using the address match table.

Abstract translation: 一种存储器件，包括接口器件和多个存储器阵列。 所述接口装置包括地址匹配表，所述地址匹配表至少包括与备用存储器位置对应的修改地址，以及控制模块，被配置为在运行时操作期间从耦合到所述主机控制器的地址命令总线从所述地址流确定地址信息。 控制模块被配置为比较来自地址流的每个地址，并且确定每个地址是否与地址匹配表中的存储地址相匹配，以识别不良地址，并将其配置为用备用存储器位置的修改地址替换坏地址。 该设备还具有多个存储器阵列。 每个存储器阵列包括多个存储单元。 存储器件具有包括多个备用存储器单元的存储器单元的备用组。 多个备用存储单元中的每一个可使用地址匹配表进行寻址。

公开(公告)号：US20150195040A1

公开(公告)日：2015-07-09

申请号：US14667236

申请日：2015-03-24

Applicant: INPHI CORPORATION

Inventor： Jamal RIANI ,  Sudeep BHOJA

IPC: H04B10/27 ,  H04L27/02 ,  H04B10/25

CPC classification number: H04B10/27 ,  H03K9/02 ,  H04B10/2504 ,  H04B10/61 ,  H04B14/004 ,  H04L27/02 ,  H04L27/06 ,  H04L27/34

Abstract: The present invention is directed to data communication system and methods. More specifically, various embodiments of the present invention provide a communication interface that is configured to transfer data at high bandwidth using nDSQ format(s) over optical communication networks. In certain embodiments, the communication interface is used by various devices, such as spine switches and leaf switches, within a spine-leaf network architecture, which allows large amount of data to be shared among servers.