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    Method of Checking the Matching of an Antenna Connected to a NFC Component and Corresponding NFC Component
    291.
    发明申请
    Method of Checking the Matching of an Antenna Connected to a NFC Component and Corresponding NFC Component 有权
    检查连接到NFC组件的天线的匹配和相应的NFC组件的方法

    公开(公告)号：US20140022143A1

    公开(公告)日：2014-01-23

    申请号：US13938024

    申请日：2013-07-09

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Alexandre Tramoni

    IPC: H01Q1/50

    CPC classification number: H01Q1/50 ,  H04B5/0043 ,  H04B5/0081 ,  H04B17/12 ,  H04B17/18 ,  H04B17/21

    Abstract: An NFC component includes a first interface that can be used in reader mode and is configured to be connected to an antenna via an impedance matching external circuit. A second interface can be used in card mode and in reader mode and is configured to be connected to the antenna and to the first interface via the impedance matching external circuit. An internal module includes a first detection circuit configured to deliver a first detection signal that represents the phase antenna matching quality when the impedance matching external circuit and the antenna are indeed connected between the first interface and the second interface. The internal module is further configured to deliver a check signal from at least the first detection signal.

    Abstract translation: NFC组件包括可以在读取器模式下使用的第一接口，并且被配置为经由阻抗匹配外部电路连接到天线。 第二接口可以用于卡模式和读卡器模式，并且被配置为通过阻抗匹配外部电路连接到天线和第一接口。 内部模块包括第一检测电路，其被配置为当阻抗匹配外部电路和天线确实连接在第一接口和第二接口之间时传送表示相位天线匹配质量的第一检测信号。 内部模块还被配置为从至少第一检测信号传递检查信号。

    LOW PASS FILTER WITH AN INCREASED DELAY
    292.
    发明申请
    LOW PASS FILTER WITH AN INCREASED DELAY 有权
    低通滤波器具有增加的延迟

    公开(公告)号：US20130278330A1

    公开(公告)日：2013-10-24

    申请号：US13868866

    申请日：2013-04-23

    Applicant: STMICROELECTRONICS (ROUSSET) SAS

    Inventor： Francois Tailliet ,  Marc Battista

    IPC: H03H11/04

    CPC classification number: H03H11/04 ,  H03K5/1252 ,  H03K5/13 ,  H03K2005/00156

    Abstract: A low pass filter comprises a filter input node configured to receive a first logic signal, a filter output node configured to supply a second logic signal, a resistive element comprising a first terminal coupled to the input node and a second terminal coupled to the output node, and a capacitive element comprising a first terminal coupled to the output node and a second terminal. The filter further comprises an inverting gate having a first terminal coupled to the input node and a second terminal coupled to the second terminal of the capacitive element.

    Abstract translation: 低通滤波器包括被配置为接收第一逻辑信号的滤波器输入节点，被配置为提供第二逻辑信号的滤波器输出节点，包括耦合到输入节点的第一终端的电阻元件和耦合到输出节点的第二终端 以及电容元件，包括耦合到所述输出节点的第一端子和第二端子。 滤波器还包括反相门，其具有耦合到输入节点的第一端子和耦合到电容元件的第二端子的第二端子。

    AUTHENTICATION OF A TERMINAL BY AN ELECTROMAGNETIC TRANSPONDER
    293.
    发明申请
    AUTHENTICATION OF A TERMINAL BY AN ELECTROMAGNETIC TRANSPONDER 有权
    电磁传感器的终端认证

    公开(公告)号：US20130257587A1

    公开(公告)日：2013-10-03

    申请号：US13900442

    申请日：2013-05-22

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Luc Wuidart

    IPC: G05B1/01

    CPC classification number: G05B1/01 ,  G06K7/10108 ,  G06K19/0723 ,  G06K19/07336 ,  G08B21/0275

    Abstract: A method of authentication of a terminal generating a magnetic field by a transponder including an oscillating circuit from which a D.C. voltage is generated, wherein at least one quantity depending on the coupling between the transponder and the terminal is compared with at least one reference value.

    Abstract translation: 一种通过包括产生直流电压的振荡电路的转发器产生磁场的终端的认证方法，其中取决于应答器和终端之间的耦合的至少一个数量与至少一个参考值进行比较。

    NONVOLATILE MEMORY COMPRISING MINI WELLS AT A FLOATING POTENTIAL
    294.
    发明申请
    NONVOLATILE MEMORY COMPRISING MINI WELLS AT A FLOATING POTENTIAL 有权
    在浮动潜能下包含微型井的非易失性存储器

    公开(公告)号：US20130250700A1

    公开(公告)日：2013-09-26

    申请号：US13786197

    申请日：2013-03-05

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Francesco La Rosa

    IPC: H01L29/788 ,  G11C16/04 ,  H01L29/66

    CPC classification number: H01L29/788 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/16 ,  H01L27/11524 ,  H01L29/66825

    Abstract: The disclosure relates to an integrated circuit comprising a nonvolatile memory on a semiconductor substrate. The integrated circuit comprises a doped isolation layer implanted in the depth of the substrate, isolated conductive trenches reaching the isolation layer and forming gates of selection transistors of memory cells, isolation trenches perpendicular to the conductive trenches and reaching the isolation layer, and conductive lines parallel to the conductive trenches, extending on the substrate and forming control gates of charge accumulation transistors of memory cells. The isolation trenches and the isolated conductive trenches delimit a plurality of mini wells in the substrate, the mini wells electrically isolated from each other, each having a floating electrical potential and comprising two memory cells.

    Abstract translation: 本公开涉及一种在半导体衬底上包括非易失性存储器的集成电路。 集成电路包括注入衬底深度的掺杂隔离层，隔离的导电沟槽到达隔离层并形成存储单元的选择晶体管的栅极，垂直于导电沟槽并到达隔离层的隔离沟槽，并且导线平行 到导电沟槽，在衬底上延伸并形成存储器单元的电荷累积晶体管的控制栅极。 隔离沟槽和隔离的导电沟槽限定了衬底中的多个微型阱，所述微型阱彼此电隔离，每个具有浮置电势并且包括两个存储单元。

    Integrated Mechanical Device for Electrical Switching
    298.
    发明申请
    Integrated Mechanical Device for Electrical Switching 有权
    集成电气开关机械装置

    公开(公告)号：US20130146873A1

    公开(公告)日：2013-06-13

    申请号：US13687932

    申请日：2012-11-28

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Pascal Fornara ,  Christian Rivero ,  Antonio di-Giacomo

    IPC: B81B3/00 ,  H01L23/58

    CPC classification number: H01H37/52 ,  B81B3/0024 ,  G01K3/005 ,  G01K5/486 ,  H01L23/58 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An integrated circuit comprising a mechanical device for electrical switching comprising a first assembly being thermally deformable and having a beam held at at least two different locations by at least two arms, the beam and the arms being metal and disposed within the same metallization level, and further comprising at least one electrically conducting body. The first assembly has a first configuration at a first temperature and a second configuration at a second temperature different from the first temperature. The beam is out of contact with the electrically conducting body in one configuration in contact with the body in the other configuration. The beam establishes or breaks an electrical link passing through the said at least one electrically conducting body and through the said beam in the different configurations.

    Abstract translation: 一种集成电路，包括用于电开关的机械装置，包括可热变形的第一组件，并且具有通过至少两个臂保持在至少两个不同位置处的梁，所述梁和所述臂是金属并且设置在相同的金属化水平内，以及 还包括至少一个导电体。 第一组件具有在第一温度下的第一构型和在与第一温度不同的第二温度下的第二构型。 在与另一种结构中的身体接触的一种结构中，光束与导电体脱离接触。 光束建立或断开通过所述至少一个导电体并通过所述光束的不同构造的电连接。

    CLOCK SIGNAL SYNCHRONIZATION AND DISTURBANCE DETECTOR
    299.
    发明申请
    CLOCK SIGNAL SYNCHRONIZATION AND DISTURBANCE DETECTOR 有权
    时钟信号同步和干扰检测器

    公开(公告)号：US20130127549A1

    公开(公告)日：2013-05-23

    申请号：US13670304

    申请日：2012-11-06

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Philippe Dreux

    IPC: H03K3/03

    CPC classification number: G06F21/75 ,  H03K3/0231 ,  H03K3/0315 ,  H03K3/354 ,  H03L7/0995

    Abstract: An electronic circuit including two ring oscillators, wherein the output of each ring oscillator is looped back on the input of this same oscillator as well on the input of the other oscillator. The application of such a circuit to the detection of a dynamic disturbance.

    Abstract translation: 包括两个环形振荡器的电子电路，其中每个环形振荡器的输出在该同一振荡器的输入端以及另一个振荡器的输入端环回。 这种电路应用于动态干扰的检测。

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