公开(公告)号：US20040214415A1

公开(公告)日：2004-10-28

申请号：US10758289

申请日：2004-01-15

Applicant: STMicroelectronics S.r.I. ,  OVONYX Inc.

Inventor： Fabio Pellizzer ,  Roberto Bez ,  Marina Tosi

IPC: H01L021/28

CPC classification number: H01L21/823835 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

Abstract: A process wherein an insulating region is formed in a body at least around an array portion of a semiconductor body; a gate electrode of semiconductor material is formed on top of a circuitry portion of the semiconductor body; a first silicide protection mask is formed on top of the array portion; the gate electrode and the active areas of the circuitry portion are silicided and the first silicide protection mask is removed. The first silicide protection mask (is of polysilicon and is formed simultaneously with the gate electrode. A second silicide protection mask of dielectric material covering the first silicide protection mask is formed before silicidation of the gate electrode. The second silicide protection mask is formed simultaneously with spacers formed laterally to the gate electrode.

Abstract translation: 一种绝缘区域至少在半导体本体的阵列部分周围形成在主体中的工艺; 半导体材料的栅电极形成在半导体本体的电路部分的顶部; 在阵列部分的顶部形成第一硅化物保护掩模; 栅电极和电路部分的有源区被硅化，并且去除第一硅化物保护掩模。 第一硅化物保护掩模（多晶硅，并与栅电极同时形成）在栅极电极硅化之前形成覆盖第一硅化物保护掩模的第二硅化物保护掩模，第二硅化物保护掩膜与 间隔件横向形成到栅电极。

公开(公告)号：US20040202244A1

公开(公告)日：2004-10-14

申请号：US10757368

申请日：2004-01-13

Applicant: STMicroelectronics S.r.I.

Inventor： Francesco Pappalardo ,  Agatino Pennisi

IPC: H04B001/66

CPC classification number: G06F13/423 ,  Y02D10/14 ,  Y02D10/151

Abstract: N binary signals are transmitted through a bus of m leads, where m

Abstract translation: 通过在第二信号上对第一信号进行编码，以一串时钟脉冲的节奏通过m引线的总线m

公开(公告)号：US20040174441A1

公开(公告)日：2004-09-09

申请号：US10732186

申请日：2003-12-10

Applicant: STMicroelectronics S.r.I

Inventor： Alfio Castorina ,  Sebastiano Battiato ,  Mirko Guarnera ,  Filippo Vella

IPC: H04N009/73 ,  H04N005/235 ,  H04N005/217

CPC classification number: H04N5/23293 ,  H04N9/73

Abstract: A method of processing digital video signals produced by a sensor that are to be presented on a viewfinder, the method involving: a first pair of processing operations for scaling and color interpolation; and a second pair of processing operations for the formation of a color matrix and for white balancing. The operations of at least one, and preferably of both of the pairs of processing operations are executed in a single step. The operation of white balancing is moreover performed only for one frame out of K frame in the frame sequence. The preferential application is in the construction of viewfinders for videocameras and digital still cameras.

Abstract translation: 一种处理要呈现在取景器上的由传感器产生的数字视频信号的方法，所述方法涉及：用于缩放和颜色插值的第一对处理操作; 以及用于形成彩色矩阵和用​​于白平衡的第二对处理操作。 在一个步骤中执行至少一个，优选两个处理操作对的操作。 此外，在帧序列中仅对K帧中的一帧执行白平衡的操作。 优先应用是为视频摄像机和数码相机拍摄取景器。

公开(公告)号：US20040152267A1

公开(公告)日：2004-08-05

申请号：US10715887

申请日：2003-11-18

Applicant: STMicroelectronics S.r.I.

Inventor： Paola Zuliani ,  Elisabetta Palumbo ,  Marina Scaravaggi ,  Roberto Annunziata

IPC: H01L021/336

CPC classification number: H01L27/11521 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11524

Abstract: A process for manufacturing a byte selection transistor for a matrix of non volatile memory cells organised in rows and columns integrated on a semiconductor substrate, each memory cell comprising a floating gate transistor and a selection transistor, the process providing the following steps: defining on a same semiconductor substrate respective active areas for the byte selection transistor, for the floating gate transistor and for the selection transistor split by portions of insulating layer; depositing a multilayer structure comprising at least a gate oxide layer, a first polysilicon layer, a dielectric layer on the whole substrate and a second polysilicon layer, characterised in that it comprises the following steps: removing through a traditional photolithographic technique the multilayer structure to form at least a couple of two bands developing substantially in a parallel way to the columns of the matrix of memory cells, the first band being effective to define the gate regions of the byte selection transistor and of the selection transistor, the second band being effective to define the gate region of the floating gate transistor, a portion of the first band further extending on the portion of insulating layer which is adjacent to the byte selection transistor, forming an opening in the portion up to expose the first polysilicon layer, forming a conductive layer in the opening to put said first polysilicon layer in electric contact with said second polysilicon layer.

Abstract translation: 一种用于制造用于集成在半导体衬底上的行和列组织的非易失性存储器单元的矩阵的字节选择晶体管的处理，每个存储单元包括浮置栅晶体管和选择晶体管，该过程提供以下步骤： 相同的半导体衬底用于字节选择晶体管的相应有效区域，用于浮置栅极晶体管和用于分离绝缘层的选择晶体管; 沉积包括至少栅极氧化物层，第一多晶硅层，整个衬底上的电介质层和第二多晶硅层的多层结构，其特征在于其包括以下步骤：通过传统的光刻技术去除形成的多层结构 至少两个条带基本上以并行方式发展到存储器单元矩阵的列，第一条带有效地限定字节选择晶体管和选择晶体管的栅极区域，第二条带有效地 限定浮栅晶体管的栅极区，第一带的一部分在绝缘层的与字节选择晶体管相邻的部分上进一步延伸，在该部分中形成开口以暴露第一多晶硅层，形成导电 以使所述第一多晶硅层与所述第二多晶硅层电接触。

公开(公告)号：US20040136242A1

公开(公告)日：2004-07-15

申请号：US10614693

申请日：2003-07-07

Applicant: STMicroelectronics S.r.I.

Inventor： Rino Micheloni ,  Ilaria Motta ,  Marco Capovilla

IPC: G11C005/00

CPC classification number: G11C16/12 ,  G11C5/145 ,  G11C8/08 ,  G11C2207/2227

Abstract: Voltage booster device (3) such as to selectively assume an active status and a stand-by status, said device comprising: a first terminal (15) such as to assume a respective electric potential and associated to a first capacitor (16), a second terminal (10) associated to a second capacitor (11) and selectively connectable to the first terminal (15), characterised in that it also comprises circuital means (100) for discharging the first capacitor thus reducing in module the electrical potential of the first terminal (15), the circuital means being activated to functioning when said device in the stand-by status and the second terminal (10) is disconnected from said first terminal (15).

Abstract translation: 电压升压装置（3），例如选择性地呈现活动状态和待机状态，所述装置包括：第一端子（15），以便呈现相应的电位并与第一电容器（16）相关联， 与第二电容器（11）相关并且可选择地连接到第一端子（15）的第二端子（10），其特征在于，其还包括用于对第一电容器进行放电的电路装置（100），从而减少模块中的第一电容器 当所述处于待机状态的设备和所述第二终端（10）与所述第一终端（15）断开连接时，所述电路装置被激活以起作用。

公开(公告)号：US20040124494A1

公开(公告)日：2004-07-01

申请号：US10608855

申请日：2003-06-27

Applicant: STMicroelectronics S.r.I.

Inventor： Francesco Ciovacco ,  Chiara Savardi ,  Roberto Colombo

IPC: H01L029/00

CPC classification number: H01L21/76232 ,  H01L21/3065 ,  H01L21/3086

Abstract: A process for forming trenches with an oblique profile and rounded top corners, including the steps of: in a semiconductor wafer, through a first polymerizing etch, forming depressions delimited by rounded top corners; and through a second polymerizing etch, opening trenches at the depressions. The second polymerizing etch is made in variable plasma conditions, so that the trenches have oblique walls with a constant slope.

Abstract translation: 一种用于形成具有倾斜轮廓和圆形顶角的沟槽的方法，包括以下步骤：在半导体晶片中，通过第一聚合蚀刻，形成由圆角顶角限定的凹陷; 并通过第二聚合蚀刻，在凹陷处打开沟槽。 在可变等离子体条件下进行第二次聚合蚀刻，使得沟槽具有斜率为斜率的倾斜壁。

公开(公告)号：US20040120385A1

公开(公告)日：2004-06-24

申请号：US10632566

申请日：2003-08-01

Applicant: STMicroelectronics Limited ,  STMicroelectronics S.r.I.

Inventor： Philip Mattos ,  Marco Losi

IPC: H04B001/707

CPC classification number: H04B1/7085 ,  G01S19/29 ,  G01S19/30 ,  H03H17/0664 ,  H04B1/70753 ,  H04B1/709 ,  H04B2201/70715

Abstract: A semiconductor integrated circuit for processing a plurality of received broadcast signals, such as GPS signals, is operable in two modes: acquisition and tracking. In an acquisition mode, sample reducer combines samples of a received signal for correlation with a locally generated version of a GPS code. In a tracking mode, the sampled signal is provided direct to the correlators without sample reduction. The same correlators are thereby used to increase acquisition speed.

Abstract translation: 用于处理诸如GPS信号的多个接收的广播信号的半导体集成电路可以以两种模式进行操作：采集和跟踪。 在采集模式中，采样减速器组合接收信号的样本，以便与本地生成的GPS码版本进行相关。 在跟踪模式中，采样信号直接提供给相关器而不需要样本减少。 因此，使用相同的相关器来提高采集速度。

公开(公告)号：US20040104713A1

公开(公告)日：2004-06-03

申请号：US10620310

申请日：2003-07-14

Applicant: STMicroelectronics S.r.I.

Inventor： Adalberto Mariani ,  Giulio Corva

IPC: G05F001/40

CPC classification number: H02M3/1584

Abstract: A multiphase buck type voltage regulator having at least two phases and including a first switching means that selectively connect a supply voltage to a load through a first current path; a second switching means that selectively connect said supply voltage to said load through a second current path; a first activation circuit that activates said first switching means; a first delay circuit that deactivates said first switching means after a first period of time; a second activation circuit that activates said second switching means; a second delay circuit that after a second period of time deactivates said second switching means; said first period of time depends on said supply voltage and on the output voltage; said second period of time depends on said supply voltage and on a voltage proportional to the difference of current that flows in said first and second current path.

Abstract translation: 一种具有至少两相的多相降压式电压调节器，包括：第一开关装置，其通过第一电流路径选择性地将电源电压连接到负载; 第二开关装置，其通过第二电流路径选择性地将所述电源电压连接到所述负载; 第一激活电路，其激活所述第一开关装置; 第一延迟电路，其在第一时间段之后停用所述第一切换装置; 第二激活电路，其激活所述第二开关装置; 第二延迟电路，在第二时间段之后，使所述第二开关装置失效; 所述第一时间段取决于所述电源电压和输出电压; 所述第二时间段取决于所述电源电压和与在所述第一和第二电流路径中流动的电流差成比例的电压。

公开(公告)号：US20040061168A1

公开(公告)日：2004-04-01

申请号：US10606164

申请日：2003-06-25

Applicant: STMICROELECTRONICS S.r.I

Inventor： Paolo Cappelletti ,  Paolo Ghezzi ,  Alfonso Maurelli ,  Loris Vendrame ,  Paola Zabberoni

IPC: H01L029/788

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11534 ,  H01L29/7885

Abstract: An electrically erasable and programmable memory cell is provided. The memory cell includes a floating gate MOS transistor and a bipolar transistor for injecting an electric charge into the floating gate. The floating gate transistor has a source region and a drain region formed in a first well with a channel defined between the drain and source regions, a control gate region, and a floating gate extending over the channel and the control gate region. The bipolar transistor has an emitter region formed in the first well, a base region consisting of the first well, and a collector region consisting of the channel. The memory cell includes a second well that is insulated from the first well, and the control gate region is formed in the second well. Further embodiments of the present invention provide a memory including at least one such memory cell, an electronic device including such a memory, and methods of integrating a memory cell and erasing a memory cell.

Abstract translation: 提供电可擦除和可编程的存储单元。 存储单元包括浮置栅极MOS晶体管和用于将电荷注入浮置栅极的双极晶体管。 浮置栅极晶体管具有形成在第一阱中的源极区和漏极区，沟道限定在漏极和源极区之间，控制栅极区以及在沟道和控制栅极区上延伸的浮动栅极。 双极晶体管具有形成在第一阱中的发射极区域，由第一阱构成的基极区域和由沟道组成的集电极区域。 存储单元包括与第一阱绝缘的第二阱，并且控制栅区形成在第二阱中。 本发明的另外的实施例提供了包括至少一个这样的存储单元的存储器，包括这种存储器的电子设备，以及集成存储器单元和擦除存储器单元的方法。

公开(公告)号：US20040039953A1

公开(公告)日：2004-02-26

申请号：US10460035

申请日：2003-06-10

Applicant: STMicroelectronics S.r.I.

Inventor： Pierangelo Confalonieri ,  Angelo Nagari ,  Germano Nicollini

IPC: G06F001/26 ,  G06F001/32

CPC classification number: H03K17/166 ,  H03K17/164

Abstract: A digital system comprises a digital data processing unit, at least one output buffer connected to the processing unit to generate output signals in response to digital signals arriving from the processing unit and at least one user unit connect as output buffer load. With a view to assuring that the switching current of the output buffer can be set to different values, the output buffer comprises means for fixing the switching current to a value that is substantially constant and independent of the load and means for selectively setting the value of the switching current and the processing unit comprises means for storing a predetermined parameter; said means are connected to the selective setting means for setting the values of the switching current as functions of the predetermined parameter.

Abstract translation: 数字系统包括数字数据处理单元，连接到处理单元的至少一个输出缓冲器，以响应于从处理单元到达的数字信号产生输出信号，并且至少一个用户单元作为输出缓冲器负载进行连接。 为了确保输出缓冲器的开关电流可以被设置为不同的值，输出缓冲器包括用于将开关电流固定为基本上恒定且与负载无关的值的装置和用于选择性地设置 开关电流和处理单元包括用于存储预定参数的装置; 所述装置连接到选择设定装置，用于将切换电流的值设定为预定参数的函数。