公开(公告)号：US09979935B2

公开(公告)日：2018-05-22

申请号：US15730312

申请日：2017-10-11

Applicant: STMicroelectronics International N.V.

Inventor： Mahesh Chandra ,  Brejesh Lall

IPC: H04N9/45 ,  H04N5/347 ,  H04N9/04

CPC classification number: H04N9/045 ,  H04N5/347

Abstract: An image sensor device may include an array of image sensing pixels with adjacent image sensing pixels being arranged in macropixel, and a processor coupled to the array of image sensing pixels. The processor may be configured to receive pixel signals from the array of image sensing pixels, and arrange the received pixel signals into macropixel signal sets for respective macropixels. The processor may be configured to perform, in parallel, an image enhancement operation on the received pixel signals for each macropixel signal set to generate enhanced macropixel signals, and transmit the enhanced macropixel signals.

公开(公告)号：US09971372B2

公开(公告)日：2018-05-15

申请号：US15685763

申请日：2017-08-24

Applicant: STMicroelectronics International N.V.

Inventor： Rajesh Narwal

IPC: G05F1/46 ,  G05F3/08 ,  G05F1/565 ,  H02M1/00 ,  G05F1/56

CPC classification number: G05F3/08 ,  G05F1/46 ,  G05F1/462 ,  G05F1/468 ,  G05F1/56 ,  G05F1/565 ,  H02M2001/0025

Abstract: A voltage regulator provides an output voltage, the voltage regulator configured to receive one of a plurality of different regulator reference voltages and a controller configured to provide a selection signal, the selection signal being used to control which of the regulator reference voltages the voltage regulator receives.

公开(公告)号：US09946966B2

公开(公告)日：2018-04-17

申请号：US14426146

申请日：2013-09-04

Applicant: STMicroelectronics International N.V.

Inventor： Vinko Kunc ,  Maksimilijan Stiglic ,  Kosta Kovacic

IPC: G06K19/06 ,  G06K19/07 ,  H01Q1/22

CPC classification number: G06K19/0726 ,  H01Q1/2208

Abstract: Tuning an antenna circuit of an actively transmitting tag to a frequency of an interrogator carrier signal after the tag was inserted into a host device is accomplished by detecting presence of the interrogator carrier signal at a location of the actively transmitting tag and hereafter setting capacitances of capacitors and/or inductances of coils comprised in said antenna circuit in a way that resonance of said antenna circuit is established while the antenna circuit is excited by a magnetic field of said interrogator carrier signal. This allows automatic tuning of an antenna circuit of an actively transmitting tag after it was inserted together with a miniature card into a host device, such as a mobile telephone, personal digital assistant, tablet PC and similar devices.

公开(公告)号：US20180100774A1

公开(公告)日：2018-04-12

申请号：US15289360

申请日：2016-10-10

Applicant: STMicroelectronics International N.V.

Inventor： Pratap Narayan Singh ,  Nitin Bansal

IPC: G01K15/00 ,  H01L23/34 ,  H01L29/73 ,  G01K1/14

CPC classification number: G01K15/005 ,  G01K1/14 ,  G01K7/01 ,  H01L23/34 ,  H01L23/345 ,  H01L29/73

Abstract: A localized substrate heater is configured to apply variable substrate heating to an integrated bipolar transistor. The base-to-emitter voltage (Vbe) of that bipolar transistor a varying substrate temperature settings is sensed, with the sensed Vbe processed to determine temperature coefficients of the bipolar transistor. The bipolar transistor may, for example, be a circuit component of an integrated temperature sensing circuit.

公开(公告)号：US09929728B2

公开(公告)日：2018-03-27

申请号：US15185514

申请日：2016-06-17

Applicant: STMicroelectronics International N.V.

Inventor： Ankit Agrawal

IPC: H03K17/10 ,  H01L29/786 ,  H01L29/06 ,  H01L29/78 ,  H01L27/12 ,  H01L29/10 ,  H01L27/092 ,  H03K17/687 ,  H01L29/423

CPC classification number: H03K17/102 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/42364 ,  H01L29/7838 ,  H01L29/78648 ,  H03K17/6872

Abstract: A CMOS device is formed in an FDSOI integrated circuit die. By retrieving the MOS functionality for gate voltage levels higher than its stress limits, second gate availability in these devices is being used, and hence removing the additional circuitry that would have been used for protecting the devices from such stress. Implementation in an inverter includes a PMOS transistor and an NMOS transistor. The PMOS and NMOS transistors each include a first gate coupled to the respective source terminal of the transistor. The PMOS and NMOS transistors each include a back gate coupled to the input of the inverter.

公开(公告)号：US09928458B2

公开(公告)日：2018-03-27

申请号：US15397559

申请日：2017-01-03

Applicant: STMicroelectronics International N.V.

Inventor： Vinko Kunc ,  Anton Stern ,  Kosta Kovacic ,  Albin Pevec ,  Maksimiljan Stiglic

IPC: G06K19/06 ,  G06K19/077 ,  G06K19/07

CPC classification number: G06K19/07773 ,  G06K19/0715 ,  G06K19/07749 ,  G06K19/0775

Abstract: An RFID transponder device has antenna terminals for coupling an antenna system to the device. A transmitter and a receiver are coupled to the antenna terminals. The device has at least one damping resistance connected to at least one of the antenna terminals. The at least one damping resistance is connected, depending on a voltage swing at the antenna terminals during a transmission burst period, either together with a serially connected switch in parallel to the antenna terminals that are coupled to the receiver, or together with a parallel connected switch between one of the antenna terminals and a terminal of the transmitter. A damping control is configured to activate the at least one damping resistance during a damping period after the transmission burst period by controlling the respective switch.

公开(公告)号：US20180083602A1

公开(公告)日：2018-03-22

申请号：US15460520

申请日：2017-03-16

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics SA

Inventor： Alok Kumar Tripathi ,  Amit Verma ,  Pascal Urard

IPC: H03K3/356 ,  H03K3/012 ,  H03K19/00

CPC classification number: H03K3/356104 ,  H03K3/012 ,  H03K3/35625 ,  H03K19/0002

Abstract: A synchronous retention flip-flop circuit includes a first circuit module powered by an interruptible power source and a second circuit module powered by a permanent power source. The first circuit module includes a first latch circuit and a second latch circuit which are configured to store at least one datum while the interruptible power source is supplying power. A transmission circuit operates to deliver the at least one datum to the second circuit module before an interruption of the interruptible power source. The second circuit module preserves the at least one datum during the interruption. Following an end of the interruption, a restoring circuit transfers the at least one datum from the second circuit module to the first circuit module via a single one of the first and second latch circuits.

公开(公告)号：US20180069552A1

公开(公告)日：2018-03-08

申请号：US15257693

申请日：2016-09-06

Applicant: STMicroelectronics International N.V.

Inventor： Prashant Singh

IPC: H03K19/0185 ,  H03K3/356 ,  H03K19/00

CPC classification number: H03K19/018521 ,  H03K3/356104 ,  H03K19/0013

Abstract: Disclosed herein is an low power output stage coupled between a supply node and a ground node, configured to drive an output, and controlled by first, second, and third control nodes. A current sinking circuit controlled by an input signal and configured to sink current from the first and second control nodes when the input signal transitions to a first logic level, thereby resulting in decoupling of the output stage from the ground node and sourcing of current to the output by the output stage. When the input signal transitions to a second logic level different than the first logic level, the current sinking circuit sinks current from a third control node, thereby resulting in decoupling of the output stage from the supply node and sinking of current from the output by the output stage.

公开(公告)号：US09898030B2

公开(公告)日：2018-02-20

申请号：US15207732

申请日：2016-07-12

Applicant: STMicroelectronics International N.V.

Inventor： Abhirup Lahiri

IPC: G05F3/30 ,  G05F3/26

CPC classification number: G05F3/30 ,  G05F3/262

Abstract: A reference voltage generator circuit includes a circuit that generates a complementary to absolute temperature (CTAT) voltage and a proportional to absolute temperature (PTAT) current. An output current circuit generates, from the PTAT current, a sink PTAT current sunk from a first node and a source PTAT current sourced to a second node, wherein the sink and source PTAT currents are equal. A resistor is directly connected between the first node and the second node. A divider circuit divides the CTAT voltage to generate a divided CTAT voltage applied to the first node. A voltage at the second node is a fractional bandgap reference voltage equal to a sum of the divided CTAT voltage and a voltage drop across the resistor that is proportional to a resistor current equal to the sink and source PTAT currents.

公开(公告)号：US20180020338A1

公开(公告)日：2018-01-18

申请号：US15472907

申请日：2017-03-29

Applicant: STMicroelectronics International N.V.

Inventor： Nicolas Cordier ,  Vinko Kunc ,  Maksimiljan Stiglic

IPC: H04W8/00 ,  H04B5/00 ,  H04W4/00 ,  H04W48/10

CPC classification number: H04W8/005 ,  H04B5/0025 ,  H04W4/80 ,  H04W48/10

Abstract: According to an embodiment, a method can be performed by a first active near-field communication (NFC) device. The method includes assuming a field detection mode, generating an advertisement pulse, and checking whether a predefined condition is fulfilled. If the checking determines that the predefined condition is fulfilled, the method includes assuming an active mode and communicating with an adjacent active NFC device, and, if the checking does not determine that the predefined condition is fulfilled, the method includes staying in the field detection mode and generating another advertisement pulse.