公开(公告)号：US20230124434A1

公开(公告)日：2023-04-20

申请号：US17502272

申请日：2021-10-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Wei Han ,  LiLi Chen

IPC: H02M3/158 ,  H02M1/08 ,  H02M1/00

Abstract: A method for operating a system including a voltage regulating power supply includes sensing a local voltage on a first node of the system and a remote voltage on a second node of the system. The first node and the second node are in a conductive path coupled to a load of the system. The first node is closer to a power stage of the voltage regulating power supply than the second node. The second node is closer to the load than the first node. The method includes detecting a load release event based on the local voltage, the remote voltage, and at least one predetermined threshold value.

公开(公告)号：US20230120305A1

公开(公告)日：2023-04-20

申请号：US17965888

申请日：2022-10-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： CHIA-HAO CHENG ,  RAHUL AGARWAL ,  CHINTAN BUCH ,  ARSALAN ALAM

IPC: H01L21/66 ,  H01L23/48 ,  H01L23/00 ,  H01L21/463 ,  H01L21/465 ,  H01L21/3205

Abstract: A method includes applying a temporary pad to a conductive pad of a semiconductor die. After testing the semiconductor die, the temporary pad is removed from the conductive pad.

公开(公告)号：US11630994B2

公开(公告)日：2023-04-18

申请号：US15898433

申请日：2018-02-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Khaled Hamidouche ,  Michael W LeBeane ,  Walter B Benton ,  Michael L Chu

IPC: G06N3/08 ,  G06F15/173 ,  G06N3/084 ,  G06N3/063 ,  G06N3/045

Abstract: A method of training a neural network includes, at a local computing node, receiving remote parameters from a set of one or more remote computing nodes, initiating execution of a forward pass in a local neural network in the local computing node to determine a final output based on the remote parameters, initiating execution of a backward pass in the local neural network to determine updated parameters for the local neural network, and prior to completion of the backward pass, transmitting a subset of the updated parameters to the set of remote computing nodes.

公开(公告)号：US11630667B2

公开(公告)日：2023-04-18

申请号：US16697660

申请日：2019-11-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Jiasheng Chen ,  Bin He ,  Jian Huang ,  Michael Mantor

IPC: G06F9/30 ,  G06F9/48

Abstract: A processor includes a plurality of vector sub-processors (VSPs) and a plurality of memory banks dedicated to respective VSPs. A first memory bank corresponding to a first VSP includes a first plurality of high vector general purpose register (VGPR) banks and a first plurality of low VGPR banks corresponding to the first plurality of high VGPR banks. The first memory bank further includes a plurality of operand gathering components that store operands from respective high VGPR banks and low VGPR banks. The operand gathering components are assigned to individual threads while the threads are executed by the first VSP.

公开(公告)号：US20230115819A1

公开(公告)日：2023-04-13

申请号：US17499494

申请日：2021-10-12

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： HaiKun Dong ,  Kostantinos Danny Christidis ,  Ling-Ling Wang ,  MinHua Wu ,  Gaojian Cong ,  Rui Wang

IPC: G06F13/16 ,  G06F3/06

Abstract: Systems, apparatuses, and methods for implementing duplicated registers for access by initiators across multiple semiconductor dies are disclosed. A system includes multiple initiators on multiple semiconductor dies of a chiplet processor. One of the semiconductor dies is the master die, and this master die has copies of registers which can be accessed by the multiple initiators on the multiple semiconductor dies. When a given initiator on a given secondary die generates a register access, the register access is routed to the master die and a particular duplicate copy of the register maintained for the given secondary die. From the point of view of software, the multiple semiconductor dies appear as a single die, and the multiple initiators appear as a single initiator. Multiple types of registers can be maintained by the master die, with a flush register being one of the register types.

公开(公告)号：US11625352B2

公开(公告)日：2023-04-11

申请号：US16900632

申请日：2020-06-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Guanhao Shen ,  Ravindra Nath Bhargava ,  Raghava Sravan Adidamu

IPC: G06F13/40

Abstract: A memory controller includes a command queue and an arbiter for selecting entries from the command queue for transmission to a DRAM. The arbiter transacts streaks of consecutive read commands and streaks of consecutive write commands. The arbiter has a current mode indicating the type of commands currently being transacted, and a cross mode indicating the other type. The arbiter is operable to monitor commands in the command queue for the current mode and the cross mode, and in response to designated conditions, send at least one cross-mode command to the memory interface queue while continuing to operate in the current mode. In response to an end streak condition, the arbiter swaps the current mode and the cross mode, and transacts the cross-mode command.

公开(公告)号：US11619982B2

公开(公告)日：2023-04-04

申请号：US17134952

申请日：2020-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Miguel Rodriguez ,  Stephen Victor Kosonocky ,  Peter T. Hardman

IPC: G06F1/30 ,  G05F1/565 ,  G06F1/3203

Abstract: An integrated circuit includes a plurality of tiles receiving a power supply voltage, each having a corresponding analog circuit and operates in response to a first voltage, and a hardware controller receiving a voltage identification code and provides the first voltage to each of the plurality of tiles in response thereto. The hardware controller comprises a test time controller determining coefficients of a waveform that describes an average correspondence between the power supply voltage and the first voltage for the plurality of tiles, and a boot time controller determining a respective error signal indicating an error between the waveform and a respective actual waveform for each of the plurality of tiles, and providing the respective error signal to the corresponding analog circuit of each of the plurality of tiles. The corresponding analog circuit of each of the plurality of tiles adjusts the first voltage according to the respective error signal.

公开(公告)号：US20230099256A1

公开(公告)日：2023-03-30

申请号：US17489712

申请日：2021-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul J. Moyer

IPC: G06F12/0817

Abstract: A system and method for omission of probes when requesting data stored in memory where the omission includes creating a coherence directory entry, determining whether cache line data for the coherence directory entry is a trackable pattern, and setting an indication indicating that one or more reads for the cache line data can be serviced without sending probes. A system and method for providing extra data storage capacity in a coherence directory where the extra data storage capacity includes actively tracking cache lines, invalidating the cache line and informing the coherence directory, determining whether data is a trackable pattern, updating the coherence directory that the cache line is no longer in cache, updating the coherence directory to indicate cache line data is zero, and servicing reads to the cache line from the coherence directory and supplying the specified data.

公开(公告)号：US20230097344A1

公开(公告)日：2023-03-30

申请号：US17487247

申请日：2021-09-28

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Joseph L. Greathouse ,  Alan D. Smith ,  Francisco L. Duran ,  Felix Kuehling ,  Anthony Asaro

IPC: G06F3/06 ,  G06F12/06

Abstract: Systems and methods for dynamic repartitioning of physical memory address mapping involve relocating data stored at one or more physical memory locations of one or more memory devices to another memory device or mass storage device, repartitioning one or more corresponding physical memory maps to include new mappings between physical memory addresses and physical memory locations of the one or more memory devices, then loading the relocated data back onto the one or more memory devices at physical memory locations determined by the new physical address mapping. Such dynamic repartitioning of the physical memory address mapping does not require a processing system to be rebooted and has various applications in connection with interleaving reconfiguration and error correcting code (ECC) reconfiguration of the processing system.

公开(公告)号：US20230096652A1

公开(公告)日：2023-03-30

申请号：US17489276

申请日：2021-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Richard T. Schultz

IPC: H01L27/12 ,  H01L21/84 ,  H01L23/528 ,  H01L23/48

Abstract: A system and method for efficiently creating layout for memory bit cells are described. In various implementations, cells of a library use Cross field effect transistors (FETs) that include vertically stacked gate all around (GAA) transistors with conducting channels oriented in an orthogonal direction between them. The channels of the vertically stacked transistors use opposite doping polarities. One or more of these cells use a dual polarity local interconnect power connection to receive a voltage reference level from a backside bus. For example, a power supply reference voltage level is received by a p-type device from a backside bus where the connection traverses both a p-type local interconnect layer and an n-type local interconnect layer.