公开(公告)号：US20070170540A1

公开(公告)日：2007-07-26

申请号：US11334990

申请日：2006-01-18

Applicant: Wonsuk Chung ,  Steve Zee ,  Teruo Sasagawa

Inventor： Wonsuk Chung ,  Steve Zee ,  Teruo Sasagawa

IPC: H01L29/00

CPC classification number: B81C1/00801 ,  B81B2201/047 ,  B81C2201/014 ,  G02B26/001 ,  Y10T428/31678

Abstract: The fabrication of a MEMS device such as an interferometric modulator is improved by employing an etch stop layer between a sacrificial layer and a an electrode. The etch stop may reduce undesirable over-etching of the sacrificial layer and the electrode. The etch stop layer may also serve as a barrier layer, buffer layer, and or template layer. The etch stop layer may include silicon-rich silicon nitride.

Abstract translation: 通过在牺牲层和电极之间采用蚀刻停止层来改进诸如干涉式调制器之类的MEMS器件的制造。 蚀刻停止可减少对牺牲层和电极的不希望的过蚀刻。 蚀刻停止层也可以用作阻挡层，缓冲层和/或模板层。 蚀刻停止层可以包括富硅的氮化硅。

公开(公告)号：US07223696B2

公开(公告)日：2007-05-29

申请号：US10766557

申请日：2004-01-27

Applicant: Glenn J Leedy

Inventor： Glenn J Leedy

IPC: H01L21/302 ,  H01L21/3063

CPC classification number: H01L25/50 ,  B81B2203/0127 ,  B81B2207/07 ,  B81C1/00246 ,  B81C2201/014 ,  B81C2203/075 ,  G02F1/13452 ,  G02F2001/136281 ,  G03F7/70658 ,  G11C29/006 ,  H01L21/762 ,  H01L21/76264 ,  H01L21/76289 ,  H01L21/764 ,  H01L23/481 ,  H01L23/538 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5387 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15312 ,  H01L2924/3011 ,  H01L2924/3025 ,  Y10S438/949 ,  H01L2924/00

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract translation: 由非常薄的低应力电介质材料（例如二氧化硅或氮化硅）和半导体层形成的柔性膜制造集成电路的通用方法。 半导体器件形成在膜的半导体层中。 半导体膜层最初由标准厚度的衬底形成，然后将衬底的薄表面层全部蚀刻或抛光。 在另一个版本中，柔性膜用作与其连接的常规集成电路管芯的支撑和电互连，其中互连在膜中形成多层。 多个管芯可以连接到一个这样的膜，然后将其封装成多芯片模块。 其他应用基于用于双极和MOSFET晶体管制造，低阻抗导体互连制造，平板显示器，无掩模（直写））光刻和3D IC制造的（电路）膜处理。

公开(公告)号：US07179668B2

公开(公告)日：2007-02-20

申请号：US11113554

申请日：2005-04-25

Applicant: William J. Baney ,  Dan W. Chilcott

Inventor： William J. Baney ,  Dan W. Chilcott

IPC: H01L21/00 ,  H01L21/44

CPC classification number: B81C1/00158 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C2201/014 ,  B81C2201/019 ,  G01L9/0042

Abstract: A technique for manufacturing silicon structures includes etching a cavity into a first side of an epitaxial wafer. A thickness of an epitaxial layer is selected, based on a desired depth of the etched cavity and a desired membrane thickness. The first side of the epitaxial wafer is then bonded to a first side of a handle wafer. After thinning the epitaxial wafer until only the epitaxial layer remains, desired circuitry is formed on a second side of the remaining epitaxial layer, which is opposite the first side of the epitaxial wafer.

Abstract translation: 制造硅结构的技术包括将空腔蚀刻到外延晶片的第一侧。 基于蚀刻空腔的期望深度和期望的膜厚度来选择外延层的厚度。 然后将外延晶片的第一侧接合到处理晶片的第一侧。 在使外延晶片变薄直到只剩余外延层之后，在与外延晶片的第一侧相对的剩余外延层的第二侧上形成所需的电路。

公开(公告)号：US07049164B2

公开(公告)日：2006-05-23

申请号：US10268257

申请日：2002-10-09

Applicant: Mike Bruner

Inventor： Mike Bruner

IPC: H01L21/00 ,  H01L21/461

CPC classification number: B81C1/00484 ,  B81B2201/0271 ,  B81B2203/0136 ,  B81C1/00246 ,  B81C1/00333 ,  B81C2201/0109 ,  B81C2201/014 ,  B81C2203/0136 ,  B81C2203/0735

Abstract: The current invention provides for encapsulated release structures, intermediates thereof and methods for their fabrication. The multi-layer structure has a capping layer, that preferably comprises silicon oxide and/or silicon nitride, and which is formed over an etch resistant substrate. A patterned device layer, preferably comprising silicon nitride, is embedded in a sacrificial material, preferably comprising polysilicon, and is disposed between the etch resistant substrate and the capping layer. Access trenches or holes are formed in to capping layer and the sacrificial material are selectively etched through the access trenches, such that portions of the device layer are release from sacrificial material. The etchant preferably comprises a noble gas fluoride NGF2x (wherein Ng=Xe, Kr or Ar: and where x=1, 2 or 3). After etching that sacrificial material, the access trenches are sealed to encapsulate released portions the device layer between the etch resistant substrate and the capping layer. The current invention is particularly useful for fabricating MEMS devices, multiple cavity devices and devices with multiple release features.

Abstract translation: 本发明提供了包封的释放结构，其中间体及其制备方法。 多层结构具有覆盖层，其优选地包括氧化硅和/或氮化硅，并且其形成在耐蚀刻衬底上。 优选地包括氮化硅的图案化器件层嵌入牺牲材料中，优选地包括多晶硅，并且设置在耐蚀刻衬底和覆盖层之间。 进入沟槽或孔形成在覆盖层中，并且牺牲材料通过进入沟槽被选择性地蚀刻，使得器件层的部分从牺牲材料释放。 蚀刻剂优选包含惰性气体氟化物NGF 2X（其中Ng = Xe，Kr或Ar：其中x = 1,2或3）。 在蚀刻该牺牲材料之后，进入沟槽被密封以将器件层的释放部分封装在耐蚀刻衬底和覆盖层之间。 本发明对于制造具有多个释放特征的MEMS器件，多腔器件和器件特别有用。

公开(公告)号：US06991953B1

公开(公告)日：2006-01-31

申请号：US10112962

申请日：2002-03-28

Applicant: Mike Bruner ,  Richard Yeh ,  Jim Hunter

Inventor： Mike Bruner ,  Richard Yeh ,  Jim Hunter

IPC: H01L21/308 ,  H01L21/469

CPC classification number: B81C1/00484 ,  B81B2201/0271 ,  B81B2203/0136 ,  B81C1/00246 ,  B81C1/00333 ,  B81C2201/0109 ,  B81C2201/014 ,  B81C2203/0136 ,  B81C2203/0735

Abstract: The current invention provides for encapsulated release structures, intermediates thereof and methods for their fabrication. A multi-layer structure has a capping layer, that preferably comprises silicon oxide and/or silicon nitride, and which is formed over an etch resistant substrate. A patterned device layer, preferably comprising silicon nitride, is embedded in a sacrificial material, preferably comprising poly-silicon, and is disposed between the etch resistant substrate and the capping layer. Access trenches or holes are formed in to capping layer and the sacrificial material is selectively etched through the access trenches, such that portions of the device layer are release from sacrificial material. The etchant preferably comprises a noble gas fluoride NGF2x, (wherein NG=Xe, Kr or Ar: and where x=1, 2 or 3). After etching that sacrificial material, the access trenches are sealed to encapsulate released portions the device layer between the etch resistant substrate and the capping layer. The current invention is particularly useful for fabricating MEMS devices, multiple cavity devices and devices with multiple release features.

Abstract translation: 本发明提供了包封的释放结构，其中间体及其制备方法。 多层结构具有覆盖层，其优选地包括氧化硅和/或氮化硅，并且其形成在耐蚀刻衬底上。 优选地包括氮化硅的图案化器件层嵌入牺牲材料中，优选地包括多晶硅，并且设置在耐蚀刻衬底和覆盖层之间。 进入沟槽或孔形成在覆盖层中，并且牺牲材料被选择性地蚀刻通过进入沟槽，使得器件层的部分从牺牲材料释放。 蚀刻剂优选包含惰性气体氟化物NGF 2X（其中NG = Xe，Kr或Ar：其中x = 1,2或3）。 在蚀刻该牺牲材料之后，进入沟槽被密封以将器件层的释放部分封装在耐蚀刻衬底和覆盖层之间。 本发明对于制造具有多个释放特征的MEMS器件，多腔器件和器件特别有用。

公开(公告)号：US06930364B2

公开(公告)日：2005-08-16

申请号：US09952626

申请日：2001-09-13

Applicant: Mike Bruner

Inventor： Mike Bruner

IPC: B81C1/00 ,  B81B3/00 ,  B81B7/00 ,  H01L21/46 ,  H02N1/00 ,  H03H9/24 ,  H01L27/14

CPC classification number: B81C1/00484 ,  B81B2201/0271 ,  B81B2203/0136 ,  B81C1/00246 ,  B81C1/00333 ,  B81C2201/0109 ,  B81C2201/014 ,  B81C2203/0136 ,  B81C2203/0735

Abstract: The current invention provides for encapsulated release structures, intermediates thereof and methods for their fabrication. The multi-layer structure has a capping layer, that preferably comprises silicon oxide and/or silicon nitride, and which is formed over an etch resistant substrate. A patterned device layer, preferably comprising silicon nitride, is embedded in a sacrificial material, preferably comprising polysilicon, and is disposed between the etch resistant substrate and the capping layer. Access trenches or holes are formed in to capping layer and the sacrificial material are selectively etched through the access trenches, such that portions of the device layer are release from sacrificial material. The etchant preferably comprises a noble gas fluoride NGF2x (wherein Ng=Xe, Kr or Ar: and where x=1, 2 or 3). After etching that sacrificial material, the access trenches are sealed to encapsulate released portions the device layer between the etch resistant substrate and the capping layer. The current invention is particularly useful for fabricating MEMS devices, multiple cavity devices and devices with multiple release features.

Abstract translation: 本发明提供了包封的释放结构，其中间体及其制备方法。 多层结构具有覆盖层，其优选地包括氧化硅和/或氮化硅，并且其形成在耐蚀刻衬底上。 优选地包括氮化硅的图案化器件层嵌入牺牲材料中，优选地包括多晶硅，并且设置在耐蚀刻衬底和覆盖层之间。 进入沟槽或孔形成在覆盖层中，并且牺牲材料通过进入沟槽被选择性地蚀刻，使得器件层的部分从牺牲材料释放。 蚀刻剂优选包含惰性气体氟化物NGF 2X（其中Ng = Xe，Kr或Ar：其中x = 1,2或3）。 在蚀刻该牺牲材料之后，进入沟槽被密封以将器件层的释放部分封装在耐蚀刻衬底和覆盖层之间。 本发明对于制造具有多个释放特征的MEMS器件，多腔器件和器件特别有用。

公开(公告)号：US20050016949A1

公开(公告)日：2005-01-27

申请号：US10492009

申请日：2002-09-04

Applicant: Hubert Benzel ,  Heribert Weber ,  Frank Schaefer

Inventor： Hubert Benzel ,  Heribert Weber ,  Frank Schaefer

IPC: B81B1/00 ,  B81B3/00 ,  B81C1/00 ,  H01B13/00

CPC classification number: B81C1/00047 ,  B81C1/00246 ,  B81C2201/0115 ,  B81C2201/014

Abstract: A method is proposed which will enable cavities having optically transparent walls to be produced simply and cost-effectively in a component by using standard methods of microsystems technology. For this purpose, a silicon region is first produced, which is surrounded on all sides by at least one optically transparent cladding layer. At least one opening is then produced in the cladding layer. Over this opening, the silicon surrounded by the cladding layer is dissolved out, forming a cavity within the cladding layer. In this context, the cladding layer acts as an etch barrier layer.

Abstract translation: 提出了一种通过使用微系统技术的标准方法，能够简单且成本有效地在部件中产生具有光学透明壁的空腔的方法。 为此目的，首先制造出硅区域，其通过至少一个光学透明覆层在所有侧面上被包围。 然后在包层中产生至少一个开口。 在该开口上，由包覆层包围的硅被溶出，在包覆层内形成空腔。 在本文中，包覆层用作蚀刻阻挡层。

公开(公告)号：US20040217388A1

公开(公告)日：2004-11-04

申请号：US10853848

申请日：2004-05-25

Applicant: HRL LABORATORIES, LLC

Inventor： Randall L. Kubena ,  David T. Chang

IPC: H01L027/148

CPC classification number: B81C1/0015 ,  B81B2201/0242 ,  B81C2201/014 ,  B81C2201/0191 ,  B81C2203/036 ,  G01C19/5656 ,  G01P15/0802 ,  G01P15/0894

Abstract: A MEM tunneling gyroscope assembly includes (1) a beam structure, and a mating structure defined on a first substrate or wafer; and (2) at least one contact structure, and a mating structure defined on a second substrate or wafer, the mating structure on the second substrate or wafer being of a complementary shape to the mating structure on the first substrate or wafer; and (3) a bonding layer is disposed on at least one of said mating structures for bonding the mating structure defined on the first substrate or wafer to the mating structure on the second substrate or wafer.

Abstract translation: MEM隧道陀螺仪组件包括（1）梁结构和限定在第一衬底或晶片上的配合结构; 以及（2）至少一个接触结构以及限定在第二衬底或晶片上的配合结构，所述第二衬底或晶片上的所述配合结构与所述第一衬底或晶片上的配合结构互补形状; 和（3）粘合层设置在至少一个所述配合结构上，用于将限定在第一衬底或晶片上的配合结构接合到第二衬底或晶片上的配合结构。

公开(公告)号：US20040197526A1

公开(公告)日：2004-10-07

申请号：US10786824

申请日：2004-02-24

Applicant: HRL LABORATORIES, LLC

Inventor： Sarabjit Mehta

IPC: B32B003/00

CPC classification number: B81C1/00158 ,  B81C2201/014 ,  Y10T428/24479 ,  Y10T428/2462

Abstract: A process for fabricating monolithic membrane structures having air gaps is disclosed, comprising the steps of: providing a wafer; depositing and patterning a protective layer on the wafer; providing a trench in the wafer; depositing and patterning a metal in the trench; depositing and patterning a sacrificial layer on the metal; depositing and patterning a membrane pad on the sacrificial layer; providing a polymeric film on the protective layer and sacrificial layer, wherein part of the polymeric film has a tensile stress; and releasing part of the polymeric film from the protective layer and sacrificial layer, wherein the tensile stress of a portion of the polymeric film releases the portion of the polymeric film from the wafer and generates the air gap.

Abstract translation: 公开了一种用于制造具有气隙的整体膜结构的方法，包括以下步骤：提供晶片; 在晶片上沉积和图案化保护层; 在晶片中提供沟槽; 在沟槽中沉积和图案化金属; 在金属上沉积和图案化牺牲层; 在牺牲层上沉积和图案化膜垫; 在保护层和牺牲层上提供聚合物膜，其中聚合物膜的一部分具有拉伸应力; 以及从所述保护层和牺牲层释放所述聚合物膜的一部分，其中所述聚合物膜的一部分的拉伸应力从所述晶片释放所述聚合物膜的所述部分并产生所述气隙。

公开(公告)号：US06714625B1

公开(公告)日：2004-03-30

申请号：US08483731

申请日：1995-06-07

Applicant: Glenn Joseph Leedy

Inventor： Glenn Joseph Leedy

IPC: H01J3500

CPC classification number: H01L25/50 ,  B81B2203/0127 ,  B81B2207/07 ,  B81C1/00246 ,  B81C2201/014 ,  B81C2203/075 ,  G02F1/13452 ,  G02F2001/136281 ,  G03F7/70658 ,  G11C29/006 ,  H01L21/762 ,  H01L21/76264 ,  H01L21/76289 ,  H01L21/764 ,  H01L23/481 ,  H01L23/538 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5387 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15312 ,  H01L2924/3011 ,  H01L2924/3025 ,  Y10S438/949 ,  H01L2924/00

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract translation: 由非常薄的低应力电介质材料（例如二氧化硅或氮化硅）和半导体层形成的柔性膜制造集成电路的通用方法。 半导体器件形成在膜的半导体层中。 半导体膜层最初由标准厚度的衬底形成，然后将衬底的薄表面层全部蚀刻或抛光。 在另一个版本中，柔性膜用作与其连接的常规集成电路管芯的支撑和电互连，其中互连在膜中形成多层。 多个管芯可以连接到一个这样的膜，然后将其封装成多芯片模块。 其他应用基于用于双极和MOSFET晶体管制造，低阻抗导体互连制造，平板显示器，无掩模（直写））光刻和3D IC制造的（电路）膜处理。