公开(公告)号：US20040057265A1

公开(公告)日：2004-03-25

申请号：US10616413

申请日：2003-07-09

Applicant: STMicroelectronics SA ,  Laboratoire Materiaux et Microelectronique de Provence (L2MP)

Inventor： Jean-Michel Mirabel ,  Rachid Bouchakour ,  Pierre Canet ,  Romain Laffont ,  Juliano Razafindramora

IPC: G11C027/00

CPC classification number: G11C16/14

Abstract: A memory cell in an EEPROM includes a floating gate transistor that includes a first conducting terminal and a control gate. A method of controlling the memory cell includes setting a state of the memory cell by simultaneously applying voltage pulses of opposite polarities respectively to the first conducting terminal and to the control gate. The voltage pulses including a first portion having a first slope and a second portion having a second slope, wherein the second slope is based upon the polarities of the voltage pulses. The method allows the amplitude of the voltage pulses to be reduced.

Abstract translation: EEPROM中的存储单元包括具有第一导电端子和控制栅极的浮栅晶体管。 控制存储单元的方法包括：通过同时向第一导电端子和控制栅极施加相反极性的电压脉冲来设定存储单元的状态。 电压脉冲包括具有第一斜率的第一部分和具有第二斜率的第二部分，其中第二斜率基于电压脉冲的极性。 该方法允许降低电压脉冲的幅度。

公开(公告)号：US20040052144A1

公开(公告)日：2004-03-18

申请号：US10325617

申请日：2002-12-20

Applicant: STMicroelectronics N.V. ,  STMicroelectronics SA

Inventor： Freidbert Berens ,  Michael J. Thul ,  Franck Gilbert ,  Norbert Wehn

IPC: G11C007/00

CPC classification number: H03M13/6566 ,  H03M13/2771

Abstract: In a particular embodiment using a distributed architecture, the electronic device comprises a source memory means partitioned in N elementary source memories for storing a sequence of input data, processing means clocked by a clock signal and having N outputs for producing per cycle of the clock signal N data respectively associated to N input data respectively stored in the N elementary source memories at relative source addresses, N single port target memories, N interleaving tables containing for each relative source address the number of one target memory and the corresponding relative target address therein, N cells connected in a ring structure, each cell being further connected between one output of the processing means, one interleaving table, and the port of one target memory, each cell being adapted to receive data from said output of the processing means and from its two neighbouring cells or to write at least some of these received data sequentially in the associated target memory, in accordance with the contents of said interleaving tables.

Abstract translation: 在使用分布式架构的特定实施例中，电子设备包括在N个基本源存储器中分区的源存储器装置，用于存储输入数据序列，由时钟信号计时的处理装置，并具有用于产生每个时钟信号周期的N个输出 N个数据分别与N个输入数据相关联地存储在相对源地址的N个基本源存储器中，N个单端口目标存储器，N个交织表，每个相对源地址包含一个目标存储器的数目和其中的对应的相对目标地址， N个单元以环形结构连接，每个单元进一步连接在处理装置的一个输出端，一个交织表和一个目标存储器的端口之间，每个单元适于从处理装置的输出端接收数据， 两个相邻小区或者在相关联的小区中顺序地写入这些接收的数据中的至少一些 t存储器，根据所述交织表的内容。

公开(公告)号：US20040012486A1

公开(公告)日：2004-01-22

申请号：US10453454

申请日：2003-06-03

Applicant: STMicroelectronics SA

Inventor： Christophe Mani

IPC: H04Q005/22

CPC classification number: G06K7/10029 ,  G06K7/0008

Abstract: An anti-collision method to identify and select contactless electronic modules (MDL) by a terminal is provided. A module may generate a random identification number prior to a communication, and respond to a general or complementary identification request on a time slot that varies according to its identification number. A non-selected module may generate a new random identification number when it receives a complementary identification request. Thus, the time slot of a non-selected module provided in response to a complementary identification request is not statistically the same as its time slot in response to a previous identification request, and it varies according to its identification number (ID).

Abstract translation: 提供了一种通过终端识别和选择非接触电子模块（MDL）的防碰撞方法。 模块可以在通信之前生成随机标识号，并且在根据其标识号变化的时隙上响应一般或补充的标识请求。 未选择的模块可以在接收到补充标识请求时产生新的随机标识号。 因此，响应于补充识别请求而提供的未选择模块的时隙在响应于先前的识别请求时与其时隙在统计上不相同，并且根据其标识号（ID）而变化。

公开(公告)号：US20030234446A1

公开(公告)日：2003-12-25

申请号：US10371397

申请日：2003-02-20

Applicant: STMicroelectronics SA

Inventor： Jean-Luc Diot ,  Christophe Prior ,  Jerome Teysseyre ,  Jean-Pierre Moscicki

IPC: H01L023/48 ,  H01L023/28 ,  H01L021/44

CPC classification number: H01L21/565 ,  H01L23/3107 ,  H01L23/49548 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The leadframe has a perforation to form, between a central platform and a peripheral part located a certain distance apart, radiating elongate leads. The leadframe has, on its rear face that comes into contact with a bearing surface of a mold, at least one recess and a groove for connecting this recess to the perforation.

Abstract translation: 引线框架具有在中心平台和位于一定距离之间的周边部分之间形成穿孔，辐射细长的引线。 所述引线框在其与所述模具的支承表面接触的后表面上具有至少一个凹部和用于将所述凹部连接到所述穿孔的凹槽。

公开(公告)号：US20030233605A1

公开(公告)日：2003-12-18

申请号：US10424166

申请日：2003-04-25

Applicant: STMicroelectronics SA

Inventor： Charaf Hanna

IPC: G11C029/00

CPC classification number: H03M13/2785 ,  H03M13/2707 ,  H03M13/2764

Abstract: A method for interlacing digital data to reduce transmission errors includes dividing a stream of digital data into consecutive blocks of bits, and interlacing each block of bits by writing to an interlacing table. The interlacing table is arranged in the form of rows and columns of memory addresses, with a number of the rows and columns corresponding to predetermined interlacing parameters. The access sequences to the memory addresses for interlacing the blocks of bits are different from each other. The method further includes reading a block of bits in the interlacing table according to a memory addresses access sequence, and also writing bits to a consecutive block of bits according to the memory addresses access sequence during the reading.

Abstract translation: 用于交织数字数据以减少传输错误的方法包括将数字数据流划分成连续的比特块，并且通过写入交织表来交织每个比特块。 交错表以行和列的存储器地址的形式排列，其中多个行和列对应于预定的交织参数。 到用于交错位块的存储器地址的访问序列彼此不同。 该方法还包括根据存储器地址访问序列读取交织表中的位块，并且还在读取期间根据存储器地址访问顺序将位写入连续的位块。

公开(公告)号：US20030223289A1

公开(公告)日：2003-12-04

申请号：US10420533

申请日：2003-04-22

Applicant: STMicroelectronics SA

Inventor： Filipe Ganivet ,  Francesco La Rosa ,  Thierry Giovinazzi

IPC: G11C029/00

CPC classification number: G11C16/30

Abstract: An electrically erasable and programmable memory includes an array of memory cells, and a distribution line linked to a receiving terminal of an external supply voltage and to a booster circuit. The distribution line provides an internal supply voltage. The distribution line is also linked to the receiving terminal through a diode or a diode circuit simulating operation of a diode. The memory includes a regulator for triggering the booster circuit when the internal supply voltage becomes lower than a threshold so as to maintain the internal supply voltage close to the threshold when the external supply voltage is too low, at least during the reading of memory cells. The diode or the diode circuit is blocked when the external supply voltage is too low.

Abstract translation: 电可擦除和可编程存储器包括存储器单元的阵列，以及连接到外部电源电压的接收端的分配线和升压电路。 配电线路提供内部电源电压。 分配线还通过模拟二极管的操作的二极管或二极管电路与接收端相连。 存储器包括用于当内部电源电压变得低于阈值时触发升压电路的稳压器，以便至少在读取存储器单元期间，当外部电源电压太低时，内部电源电压保持接近阈值。 当外部电源电压太低时，二极管或二极管电路被阻塞。

公开(公告)号：US20030219126A1

公开(公告)日：2003-11-27

申请号：US10388324

申请日：2003-03-12

Applicant: STMicroelectronics SA

Inventor： Sylvie Wuidart

IPC: H04N007/167

CPC classification number: H04K3/41 ,  G06F21/755 ,  G06K19/07363 ,  H01L23/585 ,  H01L24/06 ,  H01L2924/12035 ,  H01L2924/13091 ,  H01L2924/14 ,  H04K3/60 ,  H04K3/825 ,  H04K2203/20 ,  H01L2924/00

Abstract: A method for scrambling current consumption of an integrated circuit, at least during execution of a confidential operation by the integrated circuit that includes reading confidential data stored therein and/or the calculation of an encryption code is provided. The charge pump is activated to generate current consumption fluctuations on the electrical power supply line of the integrated circuit, at an intensity great enough to mask the current consumption variations associated with the execution of the confidential operation.

Abstract translation: 提供一种用于加扰集成电路的电流消耗的方法，至少在由包括读取存储在其中的机密数据和/或加密代码的计算的集成电路执行机密操作期间。 电荷泵被激活以在集成电路的电源线上产生电流消耗波动，强度足以掩盖与执行机密操作相关联的当前消耗变化。

公开(公告)号：US20030218924A1

公开(公告)日：2003-11-27

申请号：US10406632

申请日：2003-04-03

Applicant: STMicroelectronics SA

Inventor： Benjamin Duval ,  Fabrice Marinet

IPC: G11C029/00

CPC classification number: G11C17/18

Abstract: A method of programming a row of antifuse memory cells includes breaking down at least N antifuse elements in the memory cells. The breakdown includes the application of a breakdown voltage to the anode of each antifuse element. The antifuse elements are broken down sequentially by groups of P antifuse elements, with P being less than N and at least equal to 1. The antifuse elements of a same group simultaneously receive the breakdown voltage. The breakdown of a next group of antifuse elements immediately takes place after the breakdown of a previous group of antifuse elements.

Abstract translation: 一种编程反熔丝存储单元的行的方法包括在存储单元中分解至少N个反熔丝元件。 击穿包括向每个反熔丝元件的阳极施加击穿电压。 反熔丝元件依次由P个反熔丝元件分组，其中P小于N并且至少等于1.同一组的反熔丝元件同时接收击穿电压。 下一组反熔丝元件的故障立即发生在上一组反熔丝元件击穿之后。

公开(公告)号：US11996465B2

公开(公告)日：2024-05-28

申请号：US17486000

申请日：2021-09-27

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Alexis Gauthier ,  Pascal Chevalier

IPC: H01L29/66 ,  H01L21/22 ,  H01L29/06 ,  H01L29/73

CPC classification number: H01L29/66234 ,  H01L21/22 ,  H01L29/0649 ,  H01L29/73

Abstract: A bipolar transistor includes a collector. The collector is produced by a process wherein a first substantially homogeneously doped layer is formed at the bottom of a cavity. A second gradually doped layer is then formed by diffusion of dopants of the first substantially homogeneously doped layer.

公开(公告)号：US11978530B2

公开(公告)日：2024-05-07

申请号：US17556039

申请日：2021-12-20

Applicant: STMicroelectronics SA

Inventor： Faress Tissafi Drissi

IPC: G11C7/24 ,  G11C11/419

CPC classification number: G11C7/24 ,  G11C11/419

Abstract: A memory includes memory cells arranged in rows and in columns, with at least one bit line for each column being coupled to the memory cells of the column. A read/write circuit is coupled to the bit lines and is configured to receive, for each column, a binary datum to be stored in one of the memory cells of the column. The read/write circuit includes, for each column, a latch configured to store a bit of a key, and an encryption circuit configured to encrypt the received binary datum with the bit of the key to provide encrypted binary datum. The read/write circuit controls the bit line to thereby store the encrypted binary datum.