公开(公告)号：US20180241395A1

公开(公告)日：2018-08-23

申请号：US15956292

申请日：2018-04-18

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Thierry Masson ,  Pawel Fiedorow

IPC: H03K19/018 ,  H03K17/693 ,  H01L29/66 ,  G06F11/20 ,  H01L29/06 ,  H03K17/16

CPC classification number: H03K19/01843 ,  G06F11/20 ,  H01L29/0661 ,  H01L29/66659 ,  H03K17/005 ,  H03K17/063 ,  H03K17/165 ,  H03K17/6874 ,  H03K17/693 ,  H03K2217/0054 ,  H03K2217/0081

Abstract: An analog multiplexer includes inputs and one output. A switching circuit is coupled between each input and the output. Each switching circuit includes an NMOS switching module, having an on state and an off state, and a control module supplied by a first supply voltage and operating to reduce leakage currents of the NMOS switching module when in the off state. The control module further operates to make the first NMOS switching module bidirectional irrespective of voltages present at the input and at the output.

公开(公告)号：US20180190512A1

公开(公告)日：2018-07-05

申请号：US15685552

申请日：2017-08-24

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Benoit Besancon ,  Alexandre Mas ,  Karine Saxod

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/552

CPC classification number: H01L21/565 ,  H01L21/4803 ,  H01L21/52 ,  H01L23/04 ,  H01L23/053 ,  H01L23/06 ,  H01L23/10 ,  H01L23/24 ,  H01L23/315 ,  H01L23/3192 ,  H01L23/42 ,  H01L23/4334 ,  H01L23/552

Abstract: A method for manufacturing a cover for an electronic package includes placing an insert having opposite faces between opposite faces of a cavity of a mold. A coating material is injected in the mold cavity around the insert. The coating material is then set to form a substrate that is overmolded around the insert and produce the cover.

公开(公告)号：US20180190511A1

公开(公告)日：2018-07-05

申请号：US15685285

申请日：2017-08-24

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Alexandre Mas ,  Benoit Besancon ,  Karine Saxod

IPC: H01L21/56 ,  H01L23/28 ,  H01L23/02

Abstract: A method for manufacturing a cover for an electronic package includes placing an electrically conductive insert (including an electrical contact surface) inside a cavity of a mold in a position such that the electrical contact surface is in contact with a face of the cavity of the mold. A coating material is injected into said cavity and set so as to produce a substrate that is overmolded around the insert and forms the cover where the electrical contact surface of the overmolded substrate is not covered by the coating material. An electronic package is then formed from a chip mounted on a carrier substrate that is covered by the cover. The electrical contact surface is located above and electrically connected to an electrical connection pad of either the chip or the carrier substrate.

公开(公告)号：US09995928B2

公开(公告)日：2018-06-12

申请号：US14928091

申请日：2015-10-30

Applicant: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED ,  STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Pascal Mellot ,  Donald Baxter

IPC: G02B26/06 ,  G01S7/497 ,  G01S7/486 ,  G01J1/44

CPC classification number: G02B26/06 ,  G01J1/44 ,  G01J2001/4466 ,  G01S7/4865 ,  G01S7/497

Abstract: A circuit may include a first circuit configured to generate a voltage signal for generating an optical pulse, the voltage signal being generated based on a phase control signal, and an array of single photon avalanche diode (SPAD) cells configured to detect a phase of the optical pulse. The circuit may include a phase control circuit configured to generate the phase control signal based upon a target phase value and the detected phase of the optical pulse.

公开(公告)号：US20180158854A1

公开(公告)日：2018-06-07

申请号：US15372017

申请日：2016-12-07

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Cedric Tubert

IPC: H01L27/146

CPC classification number: H01L27/14612

Abstract: A circuit includes a pixel structure having a photo sensitive element and a read transistor. The read transistor includes a first load path terminal coupled to the photo sensitive element, and a second load path terminal coupled to a voltage bus. The circuit also includes a first transistor having a third load path terminal coupled to a power supply node, and a fourth load path terminal configured to be coupled to a current source. The circuit further includes a first control switch coupled between the voltage bus and the fourth load path terminal of the first transistor.

公开(公告)号：US09984005B2

公开(公告)日：2018-05-29

申请号：US14840132

申请日：2015-08-31

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Jean-Philippe Fassino ,  Roland Bohrer ,  Laurent Gerard

IPC: G06F12/14 ,  G06F12/00 ,  H04L9/08 ,  G06F21/10 ,  G06F21/79 ,  G06F21/84 ,  H04N21/426

CPC classification number: G06F12/1408 ,  G06F21/10 ,  G06F21/79 ,  G06F21/84 ,  G06F2212/1052 ,  G06F2221/2141 ,  H04L9/0825 ,  H04N21/42623

Abstract: A method for secure processing of encrypted data within a receiver includes receiving a packet of encrypted compressed data and allocating a region of memory for storing a decrypted version of the packet of encrypted compressed data. The allocation is in response to, and after, reception of the encrypted compressed data. A size of the region of the memory allocated is equal to a size of the packet of encrypted compressed data that is received. The method further includes modifying a configuration of an access authorization filter for defining access rights to the allocated region, decrypting the packet of encrypted compressed data, and storing, in the allocated region, the decrypted compressed data of the packet. The aforementioned allocation, modification, decryption, and storage steps are repeated in response to each new reception of a packet of encrypted compressed data so as to dynamically modify the configuration of the access authorization filter.

公开(公告)号：US20180131863A1

公开(公告)日：2018-05-10

申请号：US15862946

申请日：2018-01-05

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Jeremie Teyssier ,  Francesco CASCIO

IPC: H04N5/232 ,  H04N5/235 ,  G06T5/00 ,  G06T5/50

CPC classification number: H04N5/23212 ,  G06T5/003 ,  G06T5/50 ,  G06T2207/10148 ,  H04N5/2356

Abstract: A method of adjusting a lens may include adjusting the lens at a first focus position, and acquiring a first image of a scene through the lens. The method may further include adjusting the lens at a second focus position, and acquiring a second image of the same scene through the lens. In addition, the method may include producing respective power spectra of the first and second images, and producing a criterion representing the ratio of the power spectra to estimate a focus error of the lens.

公开(公告)号：US20180128876A1

公开(公告)日：2018-05-10

申请号：US15867285

申请日：2018-01-10

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Bruno Fel

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/318547 ,  G01R31/318563

Abstract: A scan chain for testing a combinatorial logic circuit includes a first scan chain path of flip-flops connected to the combinatorial logic circuit for functional mode operation during runtime of the combinatorial logic circuit. A second scan chain path of flip-flops is also connected to the combinatorial logic circuit and supports both a shift mode and a capture mode. The second scan chain path operates in shift mode while the first scan chain path is connected to the combinatorial logic circuit for functional mode operation. The second scan chain is then connected to the combinatorial logic circuit when run time is interrupted and operates in capture mode to apply the test data to the combinatorial logic circuit.

公开(公告)号：US20180058920A1

公开(公告)日：2018-03-01

申请号：US15611266

申请日：2017-06-01

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Karine Saxod ,  Jean-Michel Riviere

IPC: G01J1/02 ,  H05K1/18 ,  H05K3/28 ,  G01J1/04 ,  G01V8/10

CPC classification number: G01J1/0271 ,  G01J1/0403 ,  G01V8/10 ,  H01L25/167 ,  H01L31/0203 ,  H01L31/167 ,  H05K1/18 ,  H05K3/284 ,  H05K2201/10151 ,  H05K2201/10378

Abstract: A microchip has a rear face attached to a front mounting face of a support plate. An encapsulation cover for the microchip is mounted to the support plate. The encapsulation cover includes a front wall, a peripheral wall extending from the front wall and an inside partition extending from the front wall and between opposite sides of the peripheral wall. The inside partition passes locally above the microchip to delimit two cavities. A bonding material is interposed between encapsulation cover and the support plate and microchip. An end part of the inside partition of the cover, adjacent to the front face of the microchip, include an accumulation and containment recess that is configured to at least partly receive the bonding material.

公开(公告)号：US09897653B2

公开(公告)日：2018-02-20

申请号：US15071342

申请日：2016-03-16

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Bruno Fel

IPC: G01R31/28 ,  G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/318547 ,  G01R31/318563

Abstract: A scan chain for testing a combinatorial logic circuit includes a first scan chain path of flip-flops connected to the combinatorial logic circuit for functional mode operation during runtime of the combinatorial logic circuit. A second scan chain path of flip-flops is also connected to the combinatorial logic circuit and supports both a shift mode and a capture mode. The second scan chain path operates in shift mode while the first scan chain path is connected to the combinatorial logic circuit for functional mode operation. The second scan chain is then connected to the combinatorial logic circuit when run time is interrupted and operates in capture mode to apply the test data to the combinatorial logic circuit.