公开(公告)号：US06709935B1

公开(公告)日：2004-03-23

申请号：US09817580

申请日：2001-03-26

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/66477 ,  H01L21/26506 ,  H01L29/1054 ,  H01L29/66545

Abstract: A method of forming a specialized channel region removes a sacrificial gate material and provides a semiconductor implant though the recess associated with the remove sacrificial gate material. The process can be utilized to form a silicon germanium layer in the channel region having a sharp profile in the vertical direction. Further, the silicon germanium layer can be ultra-thin. The silicon germanium channel region has increased charge mobility with respect to conventional channel regions.

Abstract translation: 形成专用沟道区的方法去除牺牲栅极材料并通过与去除的牺牲栅极材料相关联的凹槽来提供半导体注入。 该方法可用于在垂直方向具有锐利轮廓的通道区域中形成硅锗层。 此外，硅锗层可以是超薄的。 硅锗沟道区相对于常规沟道区具有增加的电荷迁移率。

公开(公告)号：US06703281B1

公开(公告)日：2004-03-09

申请号：US10274038

申请日：2002-10-21

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/6653 ,  H01L21/26506 ,  H01L21/268 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6659

Abstract: MOSFETs are fabricated with accurately defined, high and uniformly concentrated source/drain regions and extensions employing plural, sequential pre-amorphizing, implanting and laser thermal annealing steps with intervening spacer removal. Embodiments include forming sidewall spacers on a gate electrode, sequentially pre-amorphizing, ion implanting and laser thermal annealing to form deep source/drain regions, removing the sidewall spacers, and then sequentially pre-amorphizing, ion implanting and laser thermal annealing to form shallow source/drain extensions.

Abstract translation: 使用精确定义的高均匀浓度的源极/漏极区域和采用多个连续的前非晶化，注入和激光热退火步骤的间隔来制造MOSFET，并且间隔物移除。 实施例包括在栅电极上形成侧壁间隔物，顺序地预非晶化，离子注入和激光热退火以形成深源极/漏极区域，去除侧壁间隔物，然后依次预非晶化，离子注入和激光热退火以形成浅的 源/漏扩展。

公开(公告)号：US06696725B1

公开(公告)日：2004-02-24

申请号：US09527227

申请日：2000-03-16

Applicant: Judy X. An ,  Bin Yu

Inventor： Judy X. An ,  Bin Yu

IPC: H01L31119

CPC classification number: H01L29/66484 ,  H01L21/28105 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/7831

Abstract: A semiconductor device with reduced hot carrier injection and punch through is formed with a dual gate electrode comprising edge conductive portions, a central conductive portion, and dielectric sidewall spacers formed between the edge conductive portions and central conductive portion. The edge conductive portions provide high potential barriers against the active regions, thereby reducing threshold voltage roll off and leakage current.

Abstract translation: 具有减少的热载流子注入和穿通的半导体器件由双栅极电极形成，该双栅电极包括边缘导电部分，中心导电部分和形成在边缘导电部分和中心导电部分之间的电介质侧壁间隔物。 边缘导电部分提供抵抗有源区域的高电势势垒，从而降低阈值电压滚降和漏电流。

公开(公告)号：US06682973B1

公开(公告)日：2004-01-27

申请号：US10147650

申请日：2002-05-16

Applicant: Eric N. Paton ,  Qi Xiang ,  Bin Yu

Inventor： Eric N. Paton ,  Qi Xiang ,  Bin Yu

IPC: H01L218242

CPC classification number: H01L21/28185 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/02249 ,  H01L21/02255 ,  H01L21/2807 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28291 ,  H01L21/31604 ,  H01L21/31662 ,  H01L21/31691 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: A process for fabricating a semiconductor device having a high-K dielectric layer over a silicon substrate, including steps of growing on the silicon substrate an interfacial layer of a silicon-containing dielectric material; and depositing on the interfacial layer a layer comprising at least one high-K dielectric material, in which the interfacial layer is grown by laser excitation of the silicon substrate in the presence of oxygen, nitrous oxide, nitric oxide, ammonia or a mixture of two or more thereof. In one embodiment, the silicon-containing material is silicon dioxide, silicon nitride, silicon oxynitride or a mixture thereof.

Abstract translation: 一种用于制造在硅衬底上具有高K电介质层的半导体器件的方法，包括在硅衬底上生长含硅介电材料的界面层的步骤; 并且在所述界面层上沉积包含至少一种高K电介质材料的层，其中所述界面层通过在氧，一氧化二氮，一氧化氮，氨或两者的混合物的存在下通过硅衬底的激光激发而生长 或更多。 在一个实施方案中，含硅材料是二氧化硅，氮化硅，氮氧化硅或其混合物。

公开(公告)号：US06670260B1

公开(公告)日：2003-12-30

申请号：US09577332

申请日：2000-05-24

Applicant: Bin Yu ,  Ming-Ren Lin ,  Shekhar Pramanick

Inventor： Bin Yu ,  Ming-Ren Lin ,  Shekhar Pramanick

IPC: H01L21425

CPC classification number: H01L29/6659 ,  H01L29/0649 ,  H01L29/78

Abstract: A thin filmed fully-depleted silicon-on-insulator (SOI) metal oxide semiconductor field defect transistor (MOSFET) utilizes a local insulation structure. The local insulative structure includes a buried silicon dioxide region under the channel region. The MOSFET body thickness is very small and yet silicon available outside of the channel region and buried silicon dioxide region is available for sufficient depths of silicide in the source and drain regions. The buried silicon dioxide region can be formed by a trench isolation technique or a LOCOS technique.

Abstract translation: 薄膜完全耗尽的绝缘体上硅（SOI）金属氧化物半导体场缺陷晶体管（MOSFET）利用局部绝缘结构。 局部绝缘结构包括沟道区下方的埋置二氧化硅区域。 MOSFET体的厚度非常小，而在沟道区域和掩埋的二氧化硅区域之外可用的硅可用于源极和漏极区域中足够的硅化物深度。 掩埋的二氧化硅区域可以通过沟槽隔离技术或LOCOS技术形成。

公开(公告)号：US06630386B1

公开(公告)日：2003-10-07

申请号：US09618857

申请日：2000-07-18

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/324 ,  H01L29/1083 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6659

Abstract: A method of manufacturing an integrated circuit may include the steps of annealing a gate structure and a halo section disposed over a substrate using a first temperature, implanting dopants to form drain and source regions, and annealing drain and source regions at a second temperature. The second temperature is substantially less than the first temperature.

Abstract translation: 制造集成电路的方法可以包括以下步骤：使用第一温度退火设置在衬底上的栅极结构和卤素区段，注入掺杂剂以形成漏极和源极区域，以及在第二温度下退火漏极和源极区域。 第二温度基本上小于第一温度。

公开(公告)号：US06562665B1

公开(公告)日：2003-05-13

申请号：US09688903

申请日：2000-10-16

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2184

CPC classification number: H01L29/7853 ,  H01L29/42384 ,  H01L29/66795

Abstract: For fabricating a field effect transistor, a pillar of semiconductor material is formed, a recess is formed in the top surface of the pillar along the length of the pillar, a gate dielectric material is deposited on any exposed surface of the semiconductor material of the pillar including at the top surface and the first and second side surfaces of the pillar and at the sidewalls and the bottom wall of the recess, for a gate length along the length of the pillar. In addition, a gate electrode material is deposited on the gate dielectric material to surround the pillar at the top surface and the first and second side surfaces of the pillar and to fill the recess, for the gate length of the pillar. A drain and source dopant is implanted into exposed regions of the pillar to form a drain of the field effect transistor on a first side of the gate electrode material along the length of the pillar and to form a source of the field effect transistor on a second side of the gate electrode material along the length of the pillar.

Abstract translation: 为了制造场效应晶体管，形成半导体材料的柱，沿着柱的长度在柱的上表面形成凹部，栅极电介质材料沉积在柱的半导体材料的任何暴露的表面上 包括在柱的顶表面和柱的第一和第二侧表面以及凹槽的侧壁和底壁处，用于沿着柱的长度的浇口长度。 此外，栅极电极材料沉积在栅极电介质材料上，以围绕柱的上表面和柱的第一和第二侧表面处的柱，并填充凹槽以用于柱的栅极长度。 将漏极和源极掺杂剂注入到柱的暴露区域中，以在栅极电极材料的沿着该柱的长度的第一侧上形成场效应晶体管的漏极，并在第二个栅极晶体管的一端形成一个源极 沿着柱的长度的栅电极材料的侧面。

公开(公告)号：US06555439B1

公开(公告)日：2003-04-29

申请号：US10021551

申请日：2001-12-18

Applicant: Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

Inventor： Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

IPC: H01L2100

CPC classification number: H01L21/324 ,  H01L21/26513 ,  H01L21/268 ,  H01L21/28176 ,  H01L21/28211 ,  H01L29/6659

Abstract: A method of manufacturing a MOSFET semiconductor device includes forming a gate electrode over a substrate and a gate oxide between the gate electrode and the substrate, forming source/drain extensions in the substrate, and forming first and second sidewall spacers. Dopants are then implanted within the substrate to form amorphitized source/drain regions in the substrate adjacent to the sidewalls spacers. The amorphitized source/drain regions are partially recrystallized, and laser thermal annealing activates the source/drain regions. The source/drain extensions and sidewall spacers are adjacent to the gate electrode. The source/drain extensions can have a depth of about 50 to 300 angstroms, and the source/drain regions can have a depth of about 400 to 1000 angstroms. Also, the recrystallization reduces the amorphitized source/drain regions by a depth of about 20 to 100 angstroms. A semiconductor device is also disclosed.

Abstract translation: 一种制造MOSFET半导体器件的方法包括在衬底上形成栅电极和在栅电极和衬底之间形成栅极氧化物，在衬底中形成源极/漏极延伸部分，以及形成第一和第二侧壁间隔物。 然后将掺杂剂注入到衬底内以在邻近侧壁间隔物的衬底中形成非晶化的源极/漏极区。 非晶化的源极/漏极区域被部分再结晶，并且激光热退火激活源极/漏极区域。 源极/漏极延伸部和侧壁间隔物与栅电极相邻。 源极/漏极延伸部可以具有约50至300埃的深度，并且源极/漏极区域可以具有约400至1000埃的深度。 此外，重结晶将非晶化的源/漏区减少约20至100埃的深度。 还公开了一种半导体器件。

公开(公告)号：US06551888B1

公开(公告)日：2003-04-22

申请号：US10020496

申请日：2001-12-18

Applicant: Cyrus E. Tabery ,  Eric N. Paton ,  Bin Yu ,  Qi Xiang ,  Robert B. Ogle

Inventor： Cyrus E. Tabery ,  Eric N. Paton ,  Bin Yu ,  Qi Xiang ,  Robert B. Ogle

IPC: H01L21336

CPC classification number: H01L21/268 ,  H01L21/2026 ,  H01L29/6659

Abstract: A method of manufacturing a semiconductor device includes forming a gate electrode over a substrate, introducing dopants into the substrate, forming a tuning layer over at least a portion of the substrate, and activating the dopants using laser thermal annealing. The tuning layer causes an increase or a decrease in the amount of fluence absorbed by the portion of substrate below the tuning layer in comparison to an amount of fluence absorbed by a portion of substrate not covered by the tuning layer. Additional tuning layers can also be formed over the substrate.

Abstract translation: 一种制造半导体器件的方法包括在衬底上形成栅电极，将掺杂剂引入衬底中，在衬底的至少一部分上形成调谐层，并使用激光热退火激活掺杂剂。 与由调谐层未被覆盖的基板的一部分吸收的注量相比，调谐层引起由调谐层下方的基板部分吸收的注量的增加或减少。 也可以在衬底上形成附加的调谐层。

公开(公告)号：US06551886B1

公开(公告)日：2003-04-22

申请号：US09844637

申请日：2001-04-27

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/66772 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66545

Abstract: An ultra-thin body SOI MOSFET transistor and fabrication method are described which provide extended silicide depth in a gate-last process. The method utilizes the fabrication of a dummy gate, comprising insulation, which is replaced with an insulated gate after implantation, annealing, and the formation of silicide so that diffusion effects are reduced. By way of example, dummy gate stacks are created having insulating upper segments. Silicon is deposited on the wafer and planarized to expose the insulating segment. The junction is formed by implantation followed by annealing to recrystallize the silicon and to activate the junction. Silicide is then formed, to a depth which can exceed the thickness of the silicon within the SOI wafer, on the upper portion of the silicon layer. The segment of insulation is then removed and a gate is formed with a gate electrode insulated by high-k dielectric.

Abstract translation: 描述了一种超薄体SOI MOSFET晶体管和制造方法，其在栅极最后工艺中提供延长的硅化物深度。 该方法利用伪栅的制造，包括绝缘，其在植入，退火和硅化物的形成之后被绝缘栅取代，使得扩散效应降低。 作为示例，制造具有绝缘上段的虚拟栅极堆叠。 硅沉积在晶片上并平坦化以暴露绝缘段。 通过注入形成结，然后进行退火以使硅重结晶并激活连接。 然后，在硅层的上部形成硅化物，其深度可以超过SOI晶片内的硅的厚度。 然后去除绝缘区段，并且形成具有由高k电介质绝缘的栅电极的栅极。