公开(公告)号：US20180277193A1

公开(公告)日：2018-09-27

申请号：US15898034

申请日：2018-02-15

Applicant: Rambus Inc.

Inventor： Jade M. Kizer ,  Sivakumar Doraiswamy ,  Benedict Lau

IPC: G11C11/4076 ,  G11C11/4072 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G06F13/405 ,  G11C7/222 ,  G11C8/18 ,  G11C11/4063 ,  G11C11/4072 ,  G11C11/4096

Abstract: An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal. An adjustable delay circuit delays an enable signal to generate a delayed enable signal. A gate circuit generates a gated strobe signal using the delayed enable signal that masks transitions of the internal strobe signal that occur prior to a valid region of the internal strobe signal. A sample circuit samples data using the gated strobe signal.

公开(公告)号：US20180275323A1

公开(公告)日：2018-09-27

申请号：US15922026

申请日：2018-03-15

Applicant: Rambus Inc.

Inventor： Alexander C. Schneider ,  Patrick R. Gill

IPC: G02B5/18 ,  G02F1/01 ,  H04N5/345 ,  G06T7/11

CPC classification number: G02B5/1842 ,  G02F1/01 ,  G06T7/11 ,  G06T2207/20164 ,  H04N5/345

Abstract: An optical smart sensor combines a phase grating with a rolling shutting to distinguish between modulated point sources. Employing a phase grating in lieu of a lens dramatically reduces size and cost, while using timing information inherent to imaging techniques that used a rolling shutter allows the smart sensor to distinguish point sources quickly and easily using a single frame of image data.

公开(公告)号：US20180270432A1

公开(公告)日：2018-09-20

申请号：US15759963

申请日：2016-09-20

Applicant: Rambus Inc.

Inventor： Jay Endsley ,  Thomas Vogelsang ,  Craig M. Smith ,  Michael Guidash ,  Alexander C. Schneider

IPC: H04N5/378 ,  H04N5/355 ,  H04N5/235 ,  H04N5/353

CPC classification number: H04N5/378 ,  H04N5/2355 ,  H04N5/3532 ,  H04N5/35536 ,  H04N5/35554

Abstract: Signals representative of total photocharge integrated within respective image-sensor pixels are read out of the pixels after a first exposure interval that constitutes a first fraction of a frame interval. Signals in excess of a threshold level are read out of the pixels after an ensuing second exposure interval that constitutes a second fraction of the frame interval, leaving residual photocharge within the pixels. After a third exposure interval that constitutes a third fraction of the frame interval, signals representative of a combination of at least the residual photocharge and photocharge integrated within the pixels during the third exposure interval are read out of the pixels.

公开(公告)号：US20180248723A1

公开(公告)日：2018-08-30

申请号：US15889273

申请日：2018-02-06

Applicant: Rambus Inc.

Inventor： Robert E. Palmer

IPC: H04L27/01 ,  H04L25/03 ,  H04L25/06

CPC classification number: H04L27/01 ,  H04L7/041 ,  H04L7/046 ,  H04L25/03006 ,  H04L25/03273 ,  H04L25/069

Abstract: An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data clock signals to note the locations of zero crossings for one or more selected data patterns. The pattern or patterns may be selected from among those apt to produce the greatest timing error. Equalization settings may then be adjusted to align the zero crossings of the selected data patterns with the recovered edge clock signal.

公开(公告)号：US20180248661A1

公开(公告)日：2018-08-30

申请号：US15872885

申请日：2018-01-16

Applicant: Rambus Inc.

Inventor： Srinivasaraman Chandrasekaran ,  Kunal Desai

IPC: H04L1/20 ,  H04L7/10 ,  H04L7/00

CPC classification number: H04L1/205 ,  G01R31/31709 ,  G01R31/31726 ,  H04L1/241 ,  H04L1/242 ,  H04L7/0079 ,  H04L7/0083 ,  H04L7/10

Abstract: An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. The clock and data recovery circuits in the receivers can include clock control loops responsive to loop control signals to modify the selected reference clock to generate the local clock in response to selective one of (i) a corresponding data signal for normal operation or during a test, and (ii) a test signal applied to the clock control loop in which case the test clock is produced.

公开(公告)号：US10062421B2

公开(公告)日：2018-08-28

申请号：US15626097

申请日：2017-06-17

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Bret Stott ,  Benedict C. Lau

IPC: G11C8/00 ,  G11C7/10 ,  G06F13/16 ,  G06F12/00

CPC classification number: G11C7/1063 ,  G06F12/00 ,  G06F13/1689 ,  G11C7/1072

Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

公开(公告)号：US20180240520A1

公开(公告)日：2018-08-23

申请号：US15898041

申请日：2018-02-15

Applicant: Rambus Inc.

Inventor： Scott C. Best

IPC: G11C14/00 ,  G06F13/16 ,  G06F12/02 ,  G06F12/06

CPC classification number: G11C14/0018 ,  G06F12/0246 ,  G06F12/0638 ,  G06F13/1694

Abstract: A method of controlling a memory device is disclosed. The method includes receiving an address value that indicates a range of addresses within the memory device, each address within the range of addresses corresponding to storage locations within each of two distinct storage dice within the memory device. The address value is stored within a programmable register within the memory device.

公开(公告)号：US20180235077A1

公开(公告)日：2018-08-16

申请号：US15888231

申请日：2018-02-05

Applicant: Rambus Inc.

Inventor： Kyung Suk Oh ,  Ralf M. Schmitt ,  Yijiong Feng

IPC: H05K1/02 ,  H01B5/02

CPC classification number: H05K1/0216 ,  H01B5/02 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/5223 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure for delivering power is described. In some embodiments, the structure can include conductors disposed on two or more layers. Specifically, the structure can include a first set of interdigitated conductors disposed on a first layer and oriented substantially along an expected direction of current flow. At least one conductor in the first set of interdigitated conductors may be maintained at a first voltage, and at least one conductor in the first set of interdigitated conductors may be maintained at a second voltage, wherein the second voltage is different from the first voltage. The structure may further include a conducting structure disposed on a second layer, wherein the second layer is different from the first layer, and wherein at least one conductor in the conducting structure is maintained at the first voltage.

公开(公告)号：US20180210779A1

公开(公告)日：2018-07-26

申请号：US15855385

申请日：2017-12-27

Applicant: Rambus Inc.

Inventor： Yuanlong Wang ,  Frederick A. Ware

IPC: G06F11/07 ,  H03M13/00 ,  H03M13/09 ,  G06F11/10

CPC classification number: G06F11/0727 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/076 ,  G06F11/0793 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1068 ,  G06F11/1402 ,  G06F13/4286 ,  H03M13/09 ,  H03M13/29 ,  H03M13/2906 ,  H03M13/611 ,  H04L1/0003 ,  H04L1/0008 ,  H04L1/0061 ,  H04L1/08 ,  H04L1/1867 ,  H04L2001/0093

Abstract: A memory device includes a first interface that is to couple to a bidirectional link and a second interface to couple to a unidirectional link. An encoder generates first error-detection information corresponding to write data received via the bidirectional link for a write operation. An encoder generates second error-detection information corresponding to read data transmitted via the bidirectional link for a read operation. A transmitter coupled to the unidirectional link transmits the both the first and second error-detection information. A controller may receive the first and second error-detection information. Based on at least one of the first and second error-detection information, the controller may command the memory device to retry an operation.

公开(公告)号：US20180203759A1

公开(公告)日：2018-07-19

申请号：US15838161

申请日：2017-12-11

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Craig E. Hampel

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/16 ,  H03M13/09

CPC classification number: G06F11/1004 ,  G06F11/0703 ,  G06F11/073 ,  G06F11/1679 ,  H03M13/09

Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation