公开(公告)号：US20230229872A1

公开(公告)日：2023-07-20

申请号：US18125024

申请日：2023-03-22

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Sylvie WUIDART ,  Sophie MAURICE

IPC: G06K7/10

CPC classification number: G06K7/10297

Abstract: A near-field communication device operates to transmit data by near-field communications techniques to another device. The near-field communication device includes a memory that stores a message to be transmitted in an ASCII format. The message is retrieved from the memory and transmitted using the near-field communications techniques in an ASCII format.

公开(公告)号：US20230223358A1

公开(公告)日：2023-07-13

申请号：US18094069

申请日：2023-01-06

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Carlos Augusto SUAREZ SEGOVIA ,  David PARKER ,  Chantal TROUILLER ,  Alexandre MALHERBE ,  Stephan NIEL

IPC: H01L23/00 ,  H01L23/58 ,  H01L21/78

CPC classification number: H01L23/562 ,  H01L23/585 ,  H01L21/78

Abstract: Integrated circuits are supported by a semiconductor substrate wafer. Each integrated circuit includes an electrically active area. A thermally conductive protective structure is formed around the active areas of the various integrated circuits along scribe paths. The protective structure is located between the electrically active areas of the integrated circuits and a laser ablation area of the scribe paths. Separation of the integrated circuits is performed by scribing the semiconductor substrate wafer along the scribe paths. The process for scribing includes performing a laser ablation in the laser ablation area and then performing one of an etching or a physical scribing.

公开(公告)号：US20230223332A1

公开(公告)日：2023-07-13

申请号：US18118935

申请日：2023-03-08

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Abderrezak MARZAKI ,  Arnaud REGNIER ,  Stephan NIEL

IPC: H01L23/522

CPC classification number: H01L23/5223 ,  H10B41/35 ,  H01L28/91 ,  H01L28/92

Abstract: First and second wells are formed in a semiconductor substrate. First and second trenches in the first second wells, respectively, each extend vertically and include a central conductor insulated by a first insulating layer. A second insulating layer is formed on a top surface of the semiconductor substrate. The second insulating layer is selectively thinned over the second trench. A polysilicon layer is deposited on the second insulating layer and then lithographically patterned to form: a first polysilicon portion over the first well that is electrically connected to the central conductor of the first trench to form a first capacitor plate, a second capacitor plate formed by the first well; and a second polysilicon portion over the second well forming a floating gate electrode of a floating gate transistor of a memory cell having an access transistor whose control gate is formed by the central conductor of the second trench.

公开(公告)号：US11699224B2

公开(公告)日：2023-07-11

申请号：US17522541

申请日：2021-11-09

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Laurent Bidault

IPC: G06T7/00 ,  G06N3/04 ,  G06N3/08 ,  G06F18/214 ,  G06F18/2431 ,  G06V10/764 ,  G06V10/77 ,  G06V10/774 ,  G06V10/776 ,  G06V10/82

CPC classification number: G06T7/0004 ,  G06F18/214 ,  G06F18/2431 ,  G06N3/04 ,  G06N3/08 ,  G06V10/764 ,  G06V10/774 ,  G06V10/776 ,  G06V10/7715 ,  G06V10/82 ,  G06T2207/20081 ,  G06T2207/20084 ,  G06T2207/30148 ,  G06V2201/06

Abstract: A device includes image generation circuitry and convolutional-neural-network circuitry. The image generation circuitry, in operation, generates a digital image representation of a wafer defect map (WDM). The convolutional-neural-network circuitry, in operation, generates a defect classification associated with the WDM based on: the digital image representation of the WDM and a data-driven model associating WDM images with classes of a defined set of classes of wafer defects and generated using a training data set augmented based on defect pattern orientation types associated with training images.

公开(公告)号：US11696438B2

公开(公告)日：2023-07-04

申请号：US16928465

申请日：2020-07-14

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: H01L21/00 ,  H10B41/00 ,  H01L29/423 ,  G11C7/18 ,  H01L29/66 ,  G11C16/04 ,  H01L21/28 ,  G11C16/08 ,  G11C16/24 ,  H10B41/35 ,  H01L29/788

CPC classification number: H10B41/00 ,  G11C7/18 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  H01L29/40114 ,  H01L29/4236 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66825 ,  H10B41/35 ,  H01L29/7881

Abstract: An EEPROM memory integrated circuit includes memory cells arranged in a memory plane. Each memory cell includes an access transistor in series with a state transistor. Each access transistor is coupled, via its source region, to the corresponding source line and each state transistor is coupled, via its drain region, to the corresponding bit line. The floating gate of each state transistor rests on a dielectric layer having a first part with a first thickness, and a second part with a second thickness that is less than the first thickness. The second part is located on the source side of the state transistor.

公开(公告)号：US20230207449A1

公开(公告)日：2023-06-29

申请号：US18116672

申请日：2023-03-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak MARZAKI

IPC: H01L23/522 ,  H01L29/66 ,  H01L21/762 ,  H01L27/08

CPC classification number: H01L23/5223 ,  H01L29/66181 ,  H01L21/76224 ,  H01L27/0805

Abstract: A semiconductor region includes an isolating region which delimits a working area of the semiconductor region. A trench is located in the working area and further extends into the isolating region. The trench is filled by an electrically conductive central portion that is insulated from the working area by an isolating enclosure. A cover region is positioned to cover at least a first part of the filled trench, wherein the first part is located in the working area. A dielectric layer is in contact with the filled trench. A metal silicide layer is located at least on the electrically conductive central portion of a second part of the filled trench, wherein the second part is not covered by the cover region.

公开(公告)号：US20230189149A1

公开(公告)日：2023-06-15

申请号：US18077396

申请日：2022-12-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Nicolas CORDIER ,  Guillaume JAUNET

IPC: H04W52/02 ,  H04B5/02

CPC classification number: H04W52/0229 ,  H04B5/02

Abstract: In the case of a potential detection, by a first near field communication (NFC) device, of a second NFC device, a validation of this detection is performed according to the time variation gradient of at least one environmental condition of the first device. A value of one of an amplitude and an phase of a signal across an oscillating circuit of the first NFC device is compared to first thresholds to potentially detect the second NFC device. Validation of detection occurs when one of the amplitude and the phase of the signal is outside the first thresholds adjusted as a function of the time variation gradient. Validation detection also occurs when one of the amplitude and the phase of the signal adjusted as a function of the time variation gradient is outside the first thresholds.

公开(公告)号：US11670385B2

公开(公告)日：2023-06-06

申请号：US17558123

申请日：2021-12-21

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Chama Ameziane El Hassani

IPC: G11C16/32 ,  G11C16/10

CPC classification number: G11C16/32 ,  G11C16/10

Abstract: A method for writing to electrically erasable and programmable non-volatile memory and a corresponding integrated circuit are disclosed. In an embodiment a method includes operatively connecting a filter circuit belonging to a communication interface to an oscillator circuit, wherein the communication interface is physically connected to a bus, generating, by the oscillator circuit, an oscillation signal and regulating the oscillation signal by the filter circuit so as to generate a clock signal for timing a write cycle.

公开(公告)号：US20230163754A1

公开(公告)日：2023-05-25

申请号：US18056153

申请日：2022-11-16

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Ugo MUREDDU ,  Gilles PELISSIER ,  Guillaume REYMOND

IPC: H03K5/133 ,  H03K5/156

CPC classification number: H03K5/133 ,  H03K5/1565 ,  G11C8/18

Abstract: A wobulated signal generator includes a chain of delay elements and control circuitry. The chain of delay elements includes first delay elements, second delay elements, and third delay elements. The control circuitry, in operation, enables a number of the first delay elements, disables a number of the third delay elements, and enables a selected number of the second delay elements, defining a period of time between two consecutive rising edges of a digital wobulated signal at an output of the wobulated signal generator. The control circuitry monitors an average frequency of the digitally wobulated signal, and selectively modifies the number of enabled first delay elements and the number of disabled third delay elements based on the monitored average frequency of the digitally wobulated signal.

公开(公告)号：US20230161646A1

公开(公告)日：2023-05-25

申请号：US18058648

申请日：2022-11-23

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Isabelle Carnel ,  Valerie Assemat ,  Edwin Hilkens ,  Jeremy Ribeiro De Freitas ,  Jean Claude Bini

IPC: G06F9/54 ,  G06F9/48

CPC classification number: G06F9/542 ,  G06F9/4881

Abstract: In an embodiment an integrated circuit includes a digital-signal processing unit having an event management device configured to associate respective event data items with respective trigger signals and a digital-signal processor configured to associate a respective task with an respective event data item, wherein the event management device is configured to receive the trigger signals at input terminals and, when a trigger signal is received, store the event data item associated with the received trigger signal in an event register, and wherein the digital-signal processor is configured execute the task associated with the event data item stored in the event register.