公开(公告)号：US20020149415A1

公开(公告)日：2002-10-17

申请号：US10165088

申请日：2002-06-06

Applicant: STMicroelectronics S.A.

Inventor： Philippe Bienvenu ,  Antoine Pavlin

IPC: H03K017/72

CPC classification number: H03K17/063 ,  H03K17/18

Abstract: The detection of the presence of a load associated with a power MOS transistor integrated with its control circuit, using a delay determined taking into account the detection with respect to the occurrence of a turn-off control order of the power transistor, and where the filtering time is controlled with the power transistor switching time.

公开(公告)号：US20020138797A1

公开(公告)日：2002-09-26

申请号：US10075113

申请日：2002-02-13

Applicant: STMicroelectronics S.A.

Inventor： Marc Beaujoin ,  Thomas Alofs ,  Paul Armagnat

IPC: G11C029/00 ,  G06F011/00 ,  G01R031/28

CPC classification number: G11C29/003 ,  G11C29/38

Abstract: The sequential access memory array is able to store p words each of n bits. Such p test words each made up of n test bits are written in the memory array, the p test words are extracted sequentially and, for each current word extracted, the n test bits that compose it are compared sequentially with n respective expected data bits before extracting the next test word.

Abstract translation: 顺序访问存储器阵列能够存储每个n位的p个字。 每个由n个测试位组成的这些p个测试字被写入存储器阵列中，p个测试字被顺序提取，并且对于每个当前提取的单词，组成它们的n个测试位被顺序地与n个相应的预期数据位进行比较 提取下一个测试字。

公开(公告)号：US20020127850A1

公开(公告)日：2002-09-12

申请号：US10144944

申请日：2002-05-13

Applicant: STMicroelectronics S.A.

Inventor： Christophe Verove

IPC: H01L021/4763

CPC classification number: H01L21/76832 ,  H01L21/7681

Abstract: A method of manufacturing an integrated circuit is provided. According to the method, first and second stop layers are deposited on a first dielectric layer that covers a first metallization level. The second stop layer is selectively etched with respect to the first stop layer, and the first stop layer is selectively etched with respect to the first dielectric layer. A second dielectric layer and a third stop layer are deposited. The third stop layer is selectively etched with respect to the second dielectric layer, and the first and second dielectric layers are selectively etched with respect to the stop layers so as to form trenches in the second dielectric layer and holes in the first dielectric layer. Additionally, an integrated circuit is provided that includes first and second metallization levels. A dielectric layer is located between the metallization levels, and a first stop layer is located between the dielectric layer and the second metallization level. A second stop layer is located above the first stop layer, and a third stop layer is located above the dielectric material of the second metallization level. In one preferred embodiment, lines of at least one metallization levels are made of copper, and the dielectric layer is made of an organic polymer having an electrical permittivity coefficient of less than 3.

公开(公告)号：US20020126534A1

公开(公告)日：2002-09-12

申请号：US10096531

申请日：2002-03-11

Applicant: STMicroelectronics S.A.

Inventor： David Naura ,  Bertrand Bertrand ,  Mohamad Chehadi

IPC: G11C016/04

CPC classification number: G11C16/12

Abstract: A circuit produces a voltage for the erasure or programming of a memory cell. The circuit includes a capacitor, and a discharge circuit connected to a first terminal of the capacitor. The discharge circuit includes a first transistor, a drain of which is connected to the first terminal of the capacitor. The first transistor activates the discharge circuit when a discharge signal is received by a gate of the first transistor. The discharge circuit includes a slow discharge arm and a fast discharge arm parallel-connected to the source of the first transistor. The discharge circuit produces a low discharge current or a high discharge current for discharging the capacitor as a function of an operating mode selection signal.

Abstract translation: 电路产生用于擦除或编程存储器单元的电压。 电路包括电容器和连接到电容器的第一端子的放电电路。 放电电路包括第一晶体管，其漏极连接到电容器的第一端子。 当放电信号由第一晶体管的栅极接收时，第一晶体管激活放电电路。 放电电路包括缓慢放电臂和与第一晶体管的源极并联的快速放电臂。 放电电路产生低放电电流或高放电电流，用于根据工作模式选择信号放电电容器。

公开(公告)号：US20020119625A1

公开(公告)日：2002-08-29

申请号：US09997214

申请日：2001-11-15

Applicant: STMicroelectronics S.A.

Inventor： Paola Cavaleri ,  Bruno Leconte ,  Sebastien Zink ,  Jean Devin

IPC: H01L021/336

CPC classification number: G11C16/3418 ,  G11C16/10

Abstract: A FLASH memory erasable by page includes a flash memory array containing a plurality of floating gate transistors arranged in pages, and a checking circuit for checking the threshold voltages of the floating gate transistors. Programmed transistors that have a threshold voltage less than a given threshold are reprogrammed. The checking circuit includes a non-volatile counter formed by at least one row of floating gate transistors, a reading circuit for reading the address of a page to be checked in the counter, and an incrementing circuit for incrementing the counter after a page has been checked.

Abstract translation: 可由页面擦除的闪速存储器包括包含以页面排列的多个浮置栅极晶体管的闪存阵列，以及用于检查浮置栅极晶体管的阈值电压的检查电路。 具有小于给定阈值的阈值电压的编程晶体管被重新编程。 检查电路包括由至少一行浮动栅极晶体管形成的非易失性计数器，用于读取计数器中要检查的页面的地址的读取电路和用于在页面已经被加载之后递增计数器的递增电路 检查。

公开(公告)号：US20020119620A1

公开(公告)日：2002-08-29

申请号：US10044812

申请日：2002-01-11

Applicant: STMicroelectronics S.A.

Inventor： Olivier Menut ,  Yvon Gris

IPC: H01L021/8242

CPC classification number: H01L27/10867 ,  H01L21/02667 ,  H01L21/2022 ,  H01L27/10832

Abstract: The integrated circuit comprises a semiconductor substrate SB supporting a memory cell PM of the DRAM type comprising an access transistor T and a storage capacitor TRC. The access transistor is made on the substrate, and the substrate includes a capacitive trench TRC buried beneath the transistor and forming the storage capacitor, the capacitive trench being in contact with one of the source and drain regions of the transistor.

Abstract translation: 集成电路包括支持DRAM型存储单元PM的半导体衬底SB，包括存取晶体管T和存储电容器TRC。 存取晶体管制成在衬底上，并且衬底包括埋在晶体管下面并形成存储电容器的电容沟槽TRC，电容沟槽与晶体管的源极和漏极区域之一接触。

公开(公告)号：US20020113233A1

公开(公告)日：2002-08-22

申请号：US10044286

申请日：2002-01-11

Applicant: STMICROELECTRONICS S.A.

Inventor： Olivier Menut ,  Yvon Gris

IPC: H01L031/20 ,  H01L031/036 ,  H01L029/88 ,  H01L029/04

CPC classification number: H01L27/14603 ,  H01L27/1443 ,  H01L27/14643 ,  H01L31/03529 ,  Y02E10/50

Abstract: An integrated circuit is provided that includes a substrate incorporating a semiconductor photodiode device having a p-n junction. The photodiode device includes at least one capacitive trench buried in the substrate and connected in parallel with the junction. In a preferred embodiment, the substrate is formed from silicon, and the capacitive trench includes an internal doped silicon region partially enveloped by an insulating wall that laterally separates the internal region from the substrate. Also provided is a method for fabricating an integrated circuit including a substrate that incorporates a semiconductor photodiode device having a p-n junction.

Abstract translation: 提供一种集成电路，其包括结合有具有p-n结的半导体光电二极管器件的衬底。 该光电二极管装置包括至少一个电容沟槽，该电容沟槽埋设在该衬底中，并与该结点并联连接。 在优选实施例中，衬底由硅形成，并且电容沟槽包括由绝缘壁部分包围的内部掺杂硅区域，该绝缘壁横向分离内部区域与衬底。 还提供了一种制造集成电路的方法，该集成电路包括具有p-n结的半导体光电二极管器件的衬底。

公开(公告)号：US20020109188A1

公开(公告)日：2002-08-15

申请号：US10044829

申请日：2002-01-11

Applicant: STMICROELECTRONICS S.A.

Inventor： Olivier Menut ,  Guillaume Bouche ,  Herve Jaouen

IPC: H01L027/01

CPC classification number: H01L21/76264 ,  H01L21/76283

Abstract: The semiconductor device comprises a semiconductor substrate (SB) having locally at least one zone (ZL) terminating in the surface of the substrate and entirely bordered, along its lateral edges and its bottom, by an insulating material so as to be completely isolated from the rest of the substrate. The horizontal isolating layer may be a layer of constant thickness or a crenellated layer.

Abstract translation: 半导体器件包括半导体衬底（SB），其具有局部至少一个区域（ZL），该区域（ZL）终止于衬底的表面，并且沿着其侧边缘及其底部通过绝缘材料整齐地界定，从而与绝缘材料完全隔离 底物的剩余部分。 水平隔离层可以是恒定厚度的层或钝化层。

公开(公告)号：US20020105234A1

公开(公告)日：2002-08-08

申请号：US10059444

申请日：2002-01-29

Applicant: STMicroelectronics S.A.

Inventor： Ludovic Ruat ,  Olivier Ferrand ,  Bruno Gailhard

IPC: H02J001/00

CPC classification number: G06K7/0069 ,  G06K7/0013 ,  G06K7/006 ,  G06K7/0086 ,  Y10T307/937

Abstract: A smart card reader includes a housing for receiving a smart card, a microprocessor, and a connector for connecting the microprocessor to the received smart card for establishing communications therebetween. A voltage source provides a power supply voltage to the microprocessor based upon the smart card being received in the housing. The smart card reader further includes a first switch interposed between the voltage source and a power supply terminal of the microprocessor. The first switch is closed when the received smart card is at an end of travel in the housing so that the power supply voltage is provided to the microprocessor, and is opened when the received smart card is no longer at the end of travel in the housing so that the power supply voltage is not provided to the microprocessor.

Abstract translation: 智能卡读取器包括用于接收智能卡的壳体，微处理器和用于将微处理器连接到接收的智能卡的连接器，用于在其间建立通信。 电压源基于智能卡被接收在外壳中而向微处理器提供电源电压。 智能卡读卡器还包括插入在电压源和微处理器的电源端之间的第一开关。 当接收到的智能卡处于壳体行程结束时，第一开关闭合，使得电源电压被提供给微处理器，并且当接收到的智能卡不再在外壳中行进结束时打开 使得不向微处理器提供电源电压。

公开(公告)号：US20020097338A1

公开(公告)日：2002-07-25

申请号：US10011245

申请日：2001-12-06

Applicant: STMicroelectronics S.A.

Inventor： Pascal Voyer

IPC: H04N005/445 ,  H04N005/50

CPC classification number: H04N5/44504 ,  G09G5/06 ,  G09G5/30 ,  G09G5/393 ,  H04N9/641 ,  H04N21/435 ,  H04N21/4888

Abstract: In a method for the display of text on a screen of a television receiver, the digital data representing a received text are decoded to give, first, a list of characters to be displayed including at least one character and a color palette including at least one color, and second, a matrix of pixels associated with the list of characters to be displayed. Each element of the matrix of pixels defines the color of a corresponding point of the screen. To obtain a visual effect on at least one point of the screen, at least one color of the color palette is modified. The display method may be implemented in a television receiver.

Abstract translation: 在用于在电视接收机的屏幕上显示文本的方法中，表示接收到的文本的数字数据被解码，首先给出包括至少一个字符的显示字符列表和包括至少一个的调色板 颜色，第二，与要显示的字符列表相关联的像素矩阵。 像素矩阵的每个元素定义屏幕的对应点的颜色。 为了在屏幕的至少一个点获得视觉效果，修改调色板的至少一种颜色。 显示方法可以在电视接收机中实现。