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公开(公告)号:US12146476B2
公开(公告)日:2024-11-19
申请号:US17561605
申请日:2021-12-23
Applicant: Intel Corporation
Inventor: Jeff Ku , Mark J. Gallina , Min Suet Lim , Jianfang Zhu
Abstract: Particular embodiments described herein provide for a flexible vapor chamber with shape memory material for an electronic device. In an example, the electronic device can include a flexible vapor chamber and shape memory material coupled to the shape memory material. When the shape memory material is activated, the shape memory material moves a portion of the flexible vapor chamber to a position that helps with heat dissipation of heat collected by the flexible vapor chamber.
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公开(公告)号:US20240379495A1
公开(公告)日:2024-11-14
申请号:US18314157
申请日:2023-05-09
Applicant: Intel Corporation
Inventor: Smit KAPILA , Sumod CHERUKKATE , Abhishek SRIVASTAV , Sandesh Geejagaaru KRISHNAMURTHY , Sankarananda BASAK , Ellann COHEN , Jerrod PETERSON
IPC: H01L23/373 , H05K1/02
Abstract: The present disclosure is directed to monitoring the integrity of the thermal interface material (TIM) of a semiconductor device directly by a monitoring component of a motherboard, a system on chip (SOC), or a remote device to measure either the electrical resistivity or capacitive property of the TIM, depending on the type of TIM being used, as a means to directly assess the thermal properties (conductivity, resistance, and/or impedance) of the TIM as it ages. In an aspect, the electrical resistivity or capacitive property of the TIM may be initially measured and charted, and thereafter, the changes in the electrical resistivity or capacitive property may be sensed by the monitoring component and, based on the delta of those changes, there may be remedial actions taken to mitigate impacts to the overall system performance and/or to prevent irreparable damage to the semiconductor device/system.
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公开(公告)号:US20240378150A1
公开(公告)日:2024-11-14
申请号:US18781854
申请日:2024-07-23
Applicant: Intel Corporation
Inventor: Frank T. HADY , Sanjeev N. TRIKA
IPC: G06F12/0815 , G06F8/41 , G06F12/0804
Abstract: An apparatus is described. The apparatus includes a mass storage device processor that is to behave as an additional general purpose processing core of a computing system that a mass storage device having the mass storage device processor is to be coupled to, wherein, the mass storage device processor is to execute out of a component of main memory within the mass storage device.
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公开(公告)号:US12144110B2
公开(公告)日:2024-11-12
申请号:US17134028
申请日:2020-12-24
Applicant: Intel Corporation
Inventor: Guixiang Tan , Xiang Li , Casey Winkel , George Vergis
Abstract: An apparatus is described. The apparatus includes a printed circuit board (PCB) dual in-line memory module (DIMM) connector having ejectors. The ejectors have a small enough vertical profile to permit unbent liquid cooling conduits to run across the DIMM's semiconductor chips.
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公开(公告)号:US12142543B2
公开(公告)日:2024-11-12
申请号:US18092140
申请日:2022-12-30
Applicant: INTEL CORPORATION
Inventor: Johanna Swan , Feras Eid , Adel Elsherbini
IPC: H01L23/367 , H01L21/48 , H01L23/00 , H01L23/42 , H01L23/498
Abstract: An integrated circuit structure may be formed having a substrate, at least one integrated circuit device embedded in and electrically attached to the substrate, and a heat dissipation device in thermal contact with the integrated circuit device, wherein a first portion of the heat dissipation device extends into the substrate and wherein a second portion of the heat dissipation device extends over the substrate. In one embodiment, the heat dissipation device may comprise the first portion of the heat dissipation device formed from metallization within the substrate.
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公开(公告)号:US12142032B2
公开(公告)日:2024-11-12
申请号:US17572517
申请日:2022-01-10
Applicant: Intel Corporation
Inventor: Yuming Li , Zhen Zhou , Xiaodong Wang , Quan Yin
Abstract: An embodiment of a semiconductor package apparatus may include technology to pre-process an image to simplify a background of the image, and perform object detection on the pre-processed image with the simplified background. For example, an embodiment of a semiconductor package may include technology to pre-process an image to subtract the background from the image and perform object detection on the pre-processed image with the background subtracted. Other embodiments are disclosed and claimed.
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公开(公告)号:US12141667B2
公开(公告)日:2024-11-12
申请号:US17561480
申请日:2021-12-23
Applicant: Intel Corporation
Inventor: Patrick Hayes , Michael McCourt , Alexandra Johnson , George Ke , Scott Clark
Abstract: A disclosed example includes implementing a first worker instance and a second worker instance to operate in parallel; running a first tuning operation via the first worker instance to tune first hyperparameters; running a second tuning operation via the second worker instance using a Bayesian-based optimization to determine a hyperparameter configuration to evaluate next; evaluating the hyperparameter configuration for an external model using a surrogate model; and selecting the hyperparameter configuration for the external model.
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公开(公告)号:US20240373644A1
公开(公告)日:2024-11-07
申请号:US18778857
申请日:2024-07-19
Applicant: Intel Corporation
Inventor: Nazila Haratipour , Sou-Chi Chang , Shriram Shivaraman , I-Cheng Tung , Tobias Brown-Heft , Devin R. Merrill , Che-Yun Lin , Seung Hoon Sung , Jack Kavalieros , Uygar Avci , Matthew V. Metz
Abstract: An integrated circuit capacitor structure, includes a first electrode includes a cylindrical column, a ferroelectric layer around an exterior sidewall of the cylindrical column and a plurality of outer electrodes. The plurality of outer electrodes include a first outer electrode laterally adjacent to a first portion of an exterior of the ferroelectric layer and a second outer electrode laterally adjacent to a second portion of the exterior of the ferroelectric layer, wherein the second outer electrode is above the first outer electrode.
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公开(公告)号:US20240370972A1
公开(公告)日:2024-11-07
申请号:US18637594
申请日:2024-04-17
Applicant: Intel Corporation
Inventor: Wenyi TANG , Xu ZHANG
IPC: G06T3/4053 , G06N3/047 , G06T3/4046
Abstract: Embodiments described herein are generally directed to an end-to-end trainable degradation restoration network (DRN) that enhances the ability of a super-resolution (SR) subnetwork to deal with noisy low-resolution images. An embodiment of a method includes estimating, by a noise estimator (NE) subnetwork of the DRN, an estimated noise map for a noisy input image; and predicting, by the SR subnetwork of the DRN, a clean upscaled image based on the input image and the noise map by, for each of multiple conditional residual dense blocks (CRDBs) stacked within one or more cascade blocks representing the SR subnetwork, adjusting, by a noise control layer of the CRDB that follows a stacked set of a multiple residual dense blocks of the CRDB, feature values of an intermediate feature map associated with the input image by applying (i) a scaling factor and (ii) an offset factor derived from the noise map.
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公开(公告)号:US20240369898A1
公开(公告)日:2024-11-07
申请号:US18772564
申请日:2024-07-15
Applicant: Intel Corporation
Inventor: Jin Hong
IPC: G02F1/225 , G02F1/21 , H04B10/548
Abstract: Embodiments may relate to an electronic device that includes a modulator to modulate an in-phase portion of an input signal and a quadrature portion of the input signal. The modulator may include a III-V material on a silicon substrate. In some embodiments, the III-V material may include, for example, indium phosphide (InP). Other embodiments may be described or claimed.
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