公开(公告)号：US11481250B2

公开(公告)日：2022-10-25

申请号：US16024244

申请日：2018-06-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Alexandru Dutu ,  Matthew David Sinclair ,  Bradford Beckmann ,  David A. Wood

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38 ,  G06F9/52

Abstract: A first workgroup is preempted in response to threads in the first workgroup executing a first wait instruction including a first value of a signal and a first hint indicating a type of modification for the signal. The first workgroup is scheduled for execution on a processor core based on a first context after preemption in response to the signal having the first value. A second workgroup is scheduled for execution on the processor core based on a second context in response to preempting the first workgroup and in response to the signal having a second value. A third context it is prefetched into registers of the processor core based on the first hint and the second value. The first context is stored in a first portion of the registers and the second context is prefetched into a second portion of the registers prior to preempting the first workgroup.

公开(公告)号：US11481216B2

公开(公告)日：2022-10-25

申请号：US16126504

申请日：2018-09-10

Applicant: Advanced Micro Devices, Inc.

Inventor： Stanley Ames Lackey, Jr.

IPC: G06F9/52 ,  G06F9/30 ,  G06F9/54 ,  G06F9/46 ,  G06F9/50

Abstract: Techniques for executing an atomic command in a distributed computing network are provided. A core cluster, including a plurality of processing cores that do not natively issue atomic commands to the distributed computing network, is coupled to a translation unit. To issue an atomic command, a core requests a location in the translation unit to write an opcode and operands for the atomic command. The translation unit identifies a location (a “window”) that is not in use by another atomic command and indicates the location to the processing core. The processing core writes the opcode and operands into the window and indicates to the translation unit that the atomic command is ready. The translation generates an atomic command and issues the command to the distributed computing network for execution. After execution, the distributed computing network provides a response to the translation unit, which provides that response to the core.

公开(公告)号：US11480672B2

公开(公告)日：2022-10-25

申请号：US17125685

申请日：2020-12-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Ngoc Vinh Vu ,  Neil Patrick Kelly

IPC: G01S13/89 ,  H04N7/20 ,  G01S7/00 ,  H04N5/38 ,  G01S7/04 ,  H04N5/44 ,  G02B27/01

Abstract: Systems, apparatuses, and methods for implementing a dual-purpose millimeter-wave frequency band transmitter are disclosed. A system includes a dual-purpose transmitter sending a video stream over a wireless link to a receiver. In some embodiments, the video stream is generated as part of an augmented reality (AR) or virtual reality (VR) application. The transmitter operates in a first mode to scan and map an environment of the transmitter and receiver. The transmitter generates radio frequency (RF) signals in a first frequency range while operating in the first mode. Additionally, the transmitter operates in a second mode to send video data to the receiver, and the transmitter generates RF signals in the first frequency range while operating in the second mode.

公开(公告)号：US11474703B2

公开(公告)日：2022-10-18

申请号：US17199949

申请日：2021-03-12

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Yi Xu ,  Nuwan S. Jayasena ,  Yuan Xie

IPC: G06F3/06 ,  G06F13/16 ,  G06F12/02 ,  G06F13/42 ,  G06F1/3203 ,  G11C7/10

Abstract: An integrated circuit device includes a memory controller coupleable to a memory. The memory controller to schedule memory accesses to regions of the memory based on memory timing parameters specific to the regions. A method includes receiving a memory access request at a memory device. The method further includes accessing, from a timing data store of the memory device, data representing a memory timing parameter specific to a region of the memory cell circuitry targeted by the memory access request. The method also includes scheduling, at the memory controller, the memory access request based on the data.

公开(公告)号：US11470004B2

公开(公告)日：2022-10-11

申请号：US17027914

申请日：2020-09-22

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Narendra Kamat

IPC: H04L47/127 ,  H04L43/067 ,  H04L43/0876 ,  H04L43/16 ,  H04L47/10 ,  H04L47/30

Abstract: Graded throttling for network-on-chip traffic, including: calculating, by an agent of a network-on-chip, a number of outstanding transactions issued by the agent; determining that the number of outstanding transactions meets a threshold; and implementing, by the agent, in response to the number of outstanding transactions meeting the threshold, a traffic throttling policy.

公开(公告)号：US11468001B1

公开(公告)日：2022-10-11

申请号：US17217792

申请日：2021-03-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Muhammad Amber Hassaan ,  Michael L. Chu ,  Ashwin Aji

IPC: G06F15/78

Abstract: A processing system includes a processing unit and a memory device. The memory device includes a processing-in-memory (PIM) module that performs processing operations on behalf of the processing unit. An instruction set architecture (ISA) of the PIM module has fewer instructions than an ISA of the processing unit. Instructions received from the processing unit are translated such that processing resources of the PIM module are virtualized. As a result, the PIM module concurrently performs processing operations for multiple threads or applications of the processing unit.

公开(公告)号：US11467650B2

公开(公告)日：2022-10-11

申请号：US15819288

申请日：2017-11-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander J. Branover

IPC: G06F1/3287 ,  G06F1/3296 ,  G06F1/3212 ,  G06F1/3206 ,  G06F1/3231 ,  G06F9/4401 ,  G06F1/3203 ,  G06F1/32

Abstract: The described embodiments include an electronic device that has a hardware controller and one or more hardware subsystems. The one or more hardware subsystems support an active state, a first low power state, and a second low power state. The first low power state and second low power states are separate low power states, with the first low power state being associated with a more rapid resumption of the active state than the second low power state. The hardware controller is configured to cause the one or more hardware subsystems to transition from the first low power state to the second low power state upon detecting an idle event that indicates that a user interaction is not likely to occur and to transition from the second low power state to the first low power state upon detecting an active event that indicates that a user interaction is likely to occur.

公开(公告)号：US20220321258A1

公开(公告)日：2022-10-06

申请号：US17219198

申请日：2021-03-31

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： SEYEDMOHAMMAD SEYEDZADEHDELCHEH

IPC: H04L1/00 ,  H03M13/11 ,  H03M13/25

Abstract: Data transmission mitigating interwire crosstalk including: dividing a data block to be transmitted from a transmitter to a receiver across a set of signal wires into sub-blocks; encoding each of the sub-blocks into a plurality of codewords; selecting, for each sub-block by a cost function, one of the codewords that is less likely to introduce interwire crosstalk; transmitting the selected codewords; and updating the cost function at the transmitter with feedback from the receiver.

公开(公告)号：US20220318151A1

公开(公告)日：2022-10-06

申请号：US17219782

申请日：2021-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Jagadish B. Kotra ,  Marko Scrbak ,  Matthew Raymond Poremba

IPC: G06F12/0891 ,  G06F12/0853 ,  G06F12/0862 ,  G06F3/06

Abstract: Devices and methods for cache prefetching are provided. A device is provided which comprises memory and a processor. The memory comprises a DRAM cache, a cache dedicated to the processor and one or more intermediate caches between the dedicated cache and the DRAM cache. The processor is configured to issue prefetch requests to prefetch data, issue data access requests to fetch the data and when one or more previously issued prefetch requests are determined to be inaccurate, issue a prefetch request to prefetch a tag, corresponding to the memory address of requested data in the DRAM cache. A tag look-up is performed at the DRAM cache without performing tag look-ups at the dedicated cache or the intermediate caches. The tag is prefetched from the DRAM cache without prefetching the requested data.

公开(公告)号：US20220318012A1

公开(公告)日：2022-10-06

申请号：US17217792

申请日：2021-03-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Muhammad Amber HASSAAN ,  Michael L. CHU ,  Ashwin AJI

IPC: G06F9/30

Abstract: A processing system includes a processing unit and a memory device. The memory device includes a processing-in-memory (PIM) module that performs processing operations on behalf of the processing unit. An instruction set architecture (ISA) of the PIM module has fewer instructions than an ISA of the processing unit. Instructions received from the processing unit are translated such that processing resources of the PIM module are virtualized. As a result, the PIM module concurrently performs processing operations for multiple threads or applications of the processing unit.