公开(公告)号：US06849897B2

公开(公告)日：2005-02-01

申请号：US10423162

申请日：2003-04-24

Applicant: Zhong Dong ,  Chuck Jang

Inventor： Zhong Dong ,  Chuck Jang

IPC: H01L21/28 ,  H01L21/314 ,  H01L21/336 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/788 ,  H01L21/28273 ,  H01L21/3144 ,  H01L21/3145 ,  H01L29/511 ,  H01L29/66825

Abstract: A thin buffer layer of SiON is formed on the top surface of the floating gate, in order to protect the polysilicon surface from attack by atomic chlorine produced during the formation of the high temperature oxide of the ONO stack. The buffer layer can also be formed on other dielectric surfaces which are otherwise subject to adverse conditions in subsequent processing, such as the nitride layer in the ONO dielectric stack.

Abstract translation: 在浮栅的顶表面上形成有薄的缓冲层SiON，以便保护多晶硅表面免受在ONO堆叠的高温氧化物形成过程中产生的原子氯的侵蚀。 缓冲层也可以形成在其它电介质表面上，否则在后续处理中会受到不利条件的影响，例如ONO电介质叠层中的氮化物层。

公开(公告)号：US20040051183A1

公开(公告)日：2004-03-18

申请号：US10330522

申请日：2002-12-27

Applicant: Promos Technologies, Inc.

Inventor： Ming-Sheng Tung ,  Yueh-Chuan Lee

IPC: H01L023/48

CPC classification number: H01L21/76897 ,  H01L23/485 ,  H01L29/66659 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a self-aligned contact structure with a locally etched conductive layer comprises the steps of: preparing a substrate formed with gate structures comprising a first conductive layer, a second conductive layer, and an insulating layer; depositing a photoresist material layer on the substrate; performing a lithographic step with a bit-line contact node photomask or a bit-line contact photomask to expose a portion of the surface of the substrate; etching the exposed second conductive layer with an etchant; removing the remaining photoresist material layer; forming a sidewall spacer on the sidewalls of each gate structure; forming a dielectric layer to cover the substrate; and performing lithographic and etching steps to remove the dielectric layer and to form self-aligned contact structure.

Abstract translation: 用局部蚀刻的导电层形成自对准接触结构的方法包括以下步骤：制备由栅极结构形成的衬底，该栅极结构包括第一导电层，第二导电层和绝缘层; 在基板上沉积光致抗蚀剂材料层; 用位线接触节点光掩模或位线接触光掩模执行光刻步骤以暴露所述衬底表面的一部分; 用蚀刻剂蚀刻暴露的第二导电层; 去除剩余的光致抗蚀剂材料层; 在每个栅极结构的侧壁上形成侧壁间隔物; 形成介电层以覆盖基板; 并执行光刻和蚀刻步骤以去除介电层并形成自对准接触结构。

公开(公告)号：US20040009672A1

公开(公告)日：2004-01-15

申请号：US10192154

申请日：2002-07-11

Applicant: ProMos Technologies, Inc.

Inventor： Jefferson Lu ,  Nien-Yu Tsai

IPC: H01L021/311

CPC classification number: H01L21/76808 ,  H01L21/0276 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76232 ,  H01L21/76804

Abstract: A method for manufacturing a semiconductor device that includes providing a substrate, providing a dielectric layer over the substrate, depositing a layer of anti-reflective coating over the dielectric layer, providing a layer of photoresist over the layer of anti-reflective coating, patterning and defining the photoresist layer to provide a plurality of photoresist structures, wherein at least two adjacent photoresist structures provide a first distance, anisotropically etching the layer of anti-reflective coating unmasked by the photoresist structures to remove only a portion of the anti-reflective coating layer, etching the anti-reflective coating to completely remove the layer of anti-reflective coating unmasked by the photoresist structures, and etching the dielectric layer to form at least one trench between the at least two adjacent photoresist structures, wherein the first distance is substantially equal to a second distance defining an opening at the top of the trench.

公开(公告)号：US20030199135A1

公开(公告)日：2003-10-23

申请号：US10437985

申请日：2003-05-15

Applicant: ProMOS Technologies Inc.

Inventor： Yueh-Chuan Lee ,  Shih-Lung Chen ,  Jin-Shing Huang ,  Wen-Sheng Lee

IPC: H01L021/8238

CPC classification number: H01L27/10861 ,  H01L21/0217 ,  H01L21/02326 ,  H01L21/02332 ,  H01L21/3144 ,  H01L27/0805

Abstract: A method of forming capacitor dielectric structure, comprising steps of providing a semiconductor substrate having at least a predetermined capacitor structure, using silicon nitride deposition to form a SiN layer on the predetermined capacitor structure, using a reoxidation process to grow an oxide layer on the SiN layer, and using a nitridation process to form a nitridation layer on the oxide layer.

Abstract translation: 一种形成电容器电介质结构的方法，包括以下步骤：提供具有至少预定电容器结构的半导体衬底，使用氮化硅沉积在预定电容器结构上形成SiN层，使用再氧化工艺在SiN上生长氧化物层 层，并且使用氮化工艺在氧化物层上形成氮化层。

公开(公告)号：US20030127696A1

公开(公告)日：2003-07-10

申请号：US10310904

申请日：2002-12-06

Applicant: ProMOS Technologies Inc.

Inventor： Brian S. Lee

IPC: H01L029/76

CPC classification number: H01L21/76843 ,  H01L21/28525 ,  H01L21/76855 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/456

Abstract: The present invention provides a metal contact of SiGe combined with cobalt silicide and cobalt. The contact resistance is greatly lowered due to both the low Schottky Barrier Height of SiGe and the low sheet resistance of cobalt silicide. The cobalt layer can serve as a glue layer and diffusion barrier layer. Thus, no additional glue layer or diffusion barrier layer needs to be formed. Moreover, the metal contact of the present invention can be integrated with a DRAM by a hybrid contact method. Implantation contact is used in pFET regions and diffusion contact is used in nFET regions. This can reduce mask steps and production costs.

Abstract translation: 本发明提供了与锗化钴和钴结合的SiGe的金属接触。 由于SiGe的低肖特基势垒高度和硅化钴的低电阻值，接触电阻大大降低。 钴层可以用作胶层和扩散阻挡层。 因此，不需要形成附加的胶层或扩散阻挡层。 此外，本发明的金属接触可以通过混合接触方法与DRAM集成。 植入接触用于pFET区域，扩散接触用于nFET区域。 这可以减少掩模步骤和生产成本。

公开(公告)号：US20030104697A1

公开(公告)日：2003-06-05

申请号：US10339157

申请日：2003-01-09

Applicant: Promos Technologies, Inc.

Inventor： Hong-Long Chang ,  Ming-Li Kung ,  Hungyueh Lu ,  Fang-Fei Liu

IPC: C25F001/00 ,  C25F003/30 ,  C25F005/00 ,  B08B006/00 ,  B08B003/00 ,  H01L021/302 ,  H01L021/461

CPC classification number: H01L21/02071 ,  H01L21/32136 ,  Y10S134/902 ,  Y10S438/906

Abstract: A dry cleaning method for use in semiconductor fabrication, including the following steps. An etched metallization structure is provided and placed in a processing chamber. The etched metallization structure is cleaned by introducing a fluorine containing gas/oxygen containing gas mixture into the processing chamber proximate the etched metallization structure without the use of a downstream microwave while applying a magnetic field proximate the etched metallization structure and maintaining a pressure of less than about 50 millitorr within the processing chamber for a predetermined time.

Abstract translation: 一种用于半导体制造的干洗方法，包括以下步骤。 提供蚀刻的金属化结构并将其放置在处理室中。 通过在邻近蚀刻的金属化结构的情况下将含氟气体/含氧气体混合物引入处理室而不使用下游微波同时在蚀刻的金属化结构附近施加磁场并保持小于等于的压力来清洁蚀刻的金属化结构 约50毫托在处理室内预定的时间。

公开(公告)号：US20030101615A1

公开(公告)日：2003-06-05

申请号：US10004680

申请日：2001-12-05

Applicant: PROMOS TECHNOLOGIES, INC.

Inventor： San-Pen Chen ,  Shun-Lian Wu ,  William Wang

IPC: F26B021/06 ,  F26B003/00

CPC classification number: H01L21/67017 ,  Y10S414/135

Abstract: An apparatus and a method for preventing a wafer mapping system of an SMIF system from being polluted by a corrosive gas remaining on wafers according to the present invention are disclosed. The wafer mapping system includes a plurality of mirrors and sensors used to detect the positions of the wafers. The apparatus of the prevent invention comprises a pipe having a plurality of holes thereon and a purge gas flowing inside the pipe, and is characterized in that the purge gas is emitted out from the plurality of holes toward the mirrors of the wafer mapping system, thereby preventing the mirrors from being polluted by the corrosive gas remaining on the wafers. The method of the prevent invention is characterized by emitting a purge gas from a pipe toward the mirrors of the wafer mapping system, thereby preventing the mirrors from being polluted by the corrosive gas remaining on the wafers.

Abstract translation: 公开了一种用于防止SMIF系统的晶片映射系统被残留在根据本发明的晶片上的腐蚀性气体污染的装置和方法。 晶片映射系统包括用于检测晶片位置的多个反射镜和传感器。 防止发明的装置包括在其上具有多个孔的管和在管内流动的净化气体，其特征在于，吹扫气体从多个孔向晶片映射系统的反射镜发射出去，从而 防止反射镜被残留在晶片上的腐蚀性气体污染。 防止发明的方法的特征在于从管道向晶片映射系统的反射镜发射净化气体，从而防止反射镜被残留在晶片上的腐蚀性气体污染。

公开(公告)号：US20030098693A1

公开(公告)日：2003-05-29

申请号：US09997135

申请日：2001-11-28

Applicant: ProMOS Technologies Inc.

Inventor： Klaus Enk

IPC: H01H031/02 ,  G01R031/26

CPC classification number: G01R31/3004 ,  G11C29/50 ,  G11C2029/5006

Abstract: The invention provides an apparatus for identifying state dependent defect related leakage currents in a tested circuit with a defect. The apparatus comprises a test system providing an input signal and an operating voltage, and a reference circuit the same as the tested circuit but without the defect receiving the input signal and the operating voltage, and operating at a first operating current, wherein, the tested circuit also receives the input signal and the operating voltage, and operates at a second operating current, and the test system senses a difference of the first and second operating current.

Abstract translation: 本发明提供一种用于在具有缺陷的测试电路中识别与状态相关的缺陷相关的泄漏电流的装置。 该装置包括提供输入信号和工作电压的测试系统以及与测试电路相同但没有接收输入信号和工作电压的缺陷并在第一工作电流下操作的参考电路，其中，测试 电路还接收输入信号和工作电压，并在第二工作电流下工作，并且测试系统检测第一和第二工作电流的差异。

公开(公告)号：US20030087492A1

公开(公告)日：2003-05-08

申请号：US10000922

申请日：2001-11-02

Applicant: PROMOS TECHNOLOGIES, INC.

Inventor： Brian Lee ,  Jan G. Zieleman

IPC: H01L021/8234 ,  H01L021/8244 ,  H01L021/8242 ,  H01L021/20

CPC classification number: H01L27/1087 ,  C07K14/43504 ,  C07K14/43595 ,  C07K2319/60 ,  H01L21/3144 ,  H01L21/31604 ,  H01L29/66181

Abstract: The present invention discloses structure and manufacturing method of binary nitride-oxide (NO) dielectric node for deep trench based DRAM devices. In the present invention, a thin strained SiGe layer is deposited prior to poly deposition to modulate the chemical potential unbalance caused by work-function (WF) differences between buried plate and poly. The thin strained SiGe layer will lower the differences by its lower band-gap characteristics at the same doping level, thereby balancing the chemical potential despite of a different doping. The modulation of the chemical potential can be achieved by a proper control of a stochimetric x value. The optimized chemical potential will assure the reliability and robustness of the dielectric node, especially the binary NO dielectric node by suppressing asymmetric charging trapping and charge injection nature.

Abstract translation: 本发明公开了用于深沟槽DRAM器件的二元氮化物（NO）介质节点的结构和制造方法。 在本发明中，在多晶沉积之前沉积薄的应变SiGe层，以调制由掩埋板和多晶硅之间的功函数（WF）差引起的化学势不平衡。 薄应变SiGe层将通过其相同掺杂水平下的较低带隙特性降低差异，从而尽管掺杂不同，仍能平衡化学势。 化学势的调制可以通过适当控制随机值x来实现。 优化的化学势将通过抑制非对称充电捕获和电荷注入性质来确保介质节点，特别是二元NO介质节点的可靠性和鲁棒性。

公开(公告)号：US20030068965A1

公开(公告)日：2003-04-10

申请号：US10126183

申请日：2002-04-19

Applicant: ProMos Technologies, Inc.

Inventor： Champion Yi

IPC: B24B001/00 ,  B24B007/19

CPC classification number: B24B49/006 ,  B24B37/04 ,  B24B41/061

Abstract: A polishing tool used for a CMP process is disclosed. The polishing tool includes a polishing platen for holding a wafer faced-up thereon and carrying the wafer to move to and fro between a first position and a second position, a polishing pad for polishing the wafer, and a holder for holding the polishing pad to self-rotate and carrying the polishing pad to move across the wafer surface and further driving the polishing pad to polish the wafer.

Abstract translation: 公开了一种用于CMP工艺的抛光工具。 抛光工具包括用于将晶片面朝上保持并将晶片在第一位置和第二位置之间来回移动的抛光台板，用于抛光晶片的抛光垫和用于保持抛光垫的保持器 自旋转并携带抛光垫移动穿过晶片表面，并进一步驱动抛光垫以抛光晶片。