公开(公告)号：US06232822B1

公开(公告)日：2001-05-15

申请号：US08268728

申请日：1994-06-30

申请人： Koji Sakui ,  Takehiro Hasegawa ,  Shigeyoshi Watanabe ,  Fujio Masuoka ,  Tsuneaki Fuse ,  Toshiki Seshita ,  Seiichi Aritome ,  Akihiro Nitayama ,  Fumio Horiguchi

发明人： Koji Sakui ,  Takehiro Hasegawa ,  Shigeyoshi Watanabe ,  Fujio Masuoka ,  Tsuneaki Fuse ,  Toshiki Seshita ,  Seiichi Aritome ,  Akihiro Nitayama ,  Fumio Horiguchi

IPC分类号： H03K17687

CPC分类号： H01L27/1025 ,  G11C11/39 ,  H01L29/36 ,  H01L29/42304 ,  H01L29/456 ,  H01L29/73 ,  H01L29/7322 ,  H01L29/885 ,  H03F3/04 ,  H03K3/021 ,  H03K17/567

摘要： A semiconductor device includes a bipolar transistor whose emitter-collector voltage is set to satisfy a condition IBE

摘要翻译： 半导体器件包括双极晶体管，其发射极 - 集电极电压被设置为满足条件IBE

公开(公告)号：US5234780A

公开(公告)日：1993-08-10

申请号：US467149

申请日：1990-01-18

申请人： Akihiro Nitayama ,  Makoto Nakase ,  Kouji Hashimoto ,  Hirotsugu Wada

发明人： Akihiro Nitayama ,  Makoto Nakase ,  Kouji Hashimoto ,  Hirotsugu Wada

IPC分类号： G03F1/00

CPC分类号： G03F1/29

摘要： An exposure mask for lithography, a method of manufacturing the same, and an exposure method using the same are disclosed. A light-transmitting opening of the exposure mask has a main light-transmitting region located in the middle of the opening and having a first optical path length, and phase shift regions adjacent to a light-shielding layer and having a second optical path length, different from the first optical path length. Light transmitted through each phase shift region interferes with light transmitted through the main light-transmitting region at the edges of the light-transmitting opening, thus enabling a sharp photo-intensity distribution of total transmitted light to be obtained. As a result, the resolution of the exposure mask is improved.

公开(公告)号：US5144579A

公开(公告)日：1992-09-01

申请号：US578608

申请日：1990-09-07

申请人： Naoko Okabe ,  Satoshi Inoue ,  Kazumasa Sunouchi ,  Takashi Yamada ,  Akihiro Nitayama ,  Hiroshi Takato

发明人： Naoko Okabe ,  Satoshi Inoue ,  Kazumasa Sunouchi ,  Takashi Yamada ,  Akihiro Nitayama ,  Hiroshi Takato

IPC分类号： H01L27/04 ,  H01L21/28 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10808

摘要： A semiconductor memory device wherein at least one of a storage node contact hole and a bit line contact hole includes a first contact hole made in a first inter-layer insulating film formed over a gate electrode and a second contact hole made in a second inter-layer insulating film formed over an electrically conductive material embedded up to a level higher than the gate electrode in the first contact hole which is contacted with the electrically conductive material, the conductive material being exposed by etching a part of the second inter-layer insulating film, whereby the size of the memory device can be made small and the reliability can be improved. Further, a capacitor is formed in a layer higher than a bit line thereby to facilitate the processing of a storage node electrode to increase the capacitor area and to improve the reliability since it is unnecessary to carry out patterning a plate electrode within a cell array. With the above construction, a short-circuiting between the embedded layers is removed and a good quality of the second inter-layer insulating film is formed.

摘要翻译： 一种半导体存储器件，其中存储节点接触孔和位线接触孔中的至少一个包括在形成在栅电极上的第一层间绝缘膜中形成的第一接触孔和在第二互连孔中形成的第二接触孔， 在导电材料上形成的层间绝缘膜，该导电材料在与导电材料接触的第一接触孔中嵌入高于栅电极的电平，通过蚀刻第二层间绝缘膜的一部分而露出导电材料 从而可以使存储器件的尺寸小并且可以提高可靠性。 此外，在高于位线的层中形成电容器，从而不需要对单元阵列内的平板电极进行图案化，便于存储节点电极的处理以增加电容器面积并提高可靠性。 利用上述结构，去除了嵌入层之间的短路，形成了第二层间绝缘膜的良好质量。

公开(公告)号：US5138412A

公开(公告)日：1992-08-11

申请号：US636556

申请日：1991-01-07

申请人： Katsuhiko Hieda ,  Akihiro Nitayama ,  Fumio Horiguchi

发明人： Katsuhiko Hieda ,  Akihiro Nitayama ,  Fumio Horiguchi

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A dynamic RAM comprises a semiconductor substrate, first and second MOS transistor formed on said semiconductor substrate, each having a source, a drain, and a gate, a first insulation film formed on said first and second MOS transistors, a first electrode formed on said first insulation film, for accumulating an electrical charge, the first electrode extending through a first hole made in the first insulation film and connected to one of the source and drain of said first MOS transistor, a second electrode formed on the first insulation film, for accumulating an electrical charge, the second electrode extending through a second hole made in the first insulation film and connected to one of the source and drain of the second MOS transistor, and at least one part of the second electrode being spaced apart from, located above, and overlapping part of the first electrode, first and second capacitor-insulating films formed on the first and second electrodes, respectively, and a capacitor electrode fromed on the first and second capacitor-insulating films and having a portion interposed between the overlapping parts of the first and second electrodes.

摘要翻译： 动态RAM包括形成在所述半导体衬底上的半导体衬底，每个具有源极，漏极和栅极的第一和第二MOS晶体管，形成在所述第一和第二MOS晶体管上的第一绝缘膜，形成在所述第一和第二MOS晶体管上的第一电极， 第一绝缘膜，用于累积电荷，所述第一电极延伸穿过由所述第一绝缘膜制成的第一孔并连接到所述第一MOS晶体管的源极和漏极中的一个，形成在所述第一绝缘膜上的第二电极，用于 累积电荷，所述第二电极延伸通过在所述第一绝缘膜中制成的第二孔并且连接到所述第二MOS晶体管的源极和漏极中的一个，并且所述第二电极的至少一部分与所述第二绝缘膜上的 以及分别形成在第一和第二电极上的第一电极，第一和第二电容器绝缘膜的重叠部分，以及电容器e 在第一和第二电容器绝缘膜上引导，并且具有插入在第一和第二电极的重叠部分之间的部分。

公开(公告)号：US5106774A

公开(公告)日：1992-04-21

申请号：US650992

申请日：1991-02-04

申请人： Katsuhiko Hieda ,  Fumio Horiguchi ,  Takeshi Hamamoto ,  Akihiro Nitayama ,  Kazumasa Sunouchi ,  Kei Kurosawa ,  Fujio Masuoka

发明人： Katsuhiko Hieda ,  Fumio Horiguchi ,  Takeshi Hamamoto ,  Akihiro Nitayama ,  Kazumasa Sunouchi ,  Kei Kurosawa ,  Fujio Masuoka

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10861 ,  H01L27/10829

摘要： A dynamic random access memory is disclosed which includes a trench type memory cell having a transistor formed in a semiconductive substrate, and a capacitor arranged in a trench formed in the substrate and having a trench structure. The capacitor includes an impurity-doped semiconductive layer formed on the substrate so as to surround the trench and having a conductivity type opposite to that of the substrate, a first capacitor electrode formed in the trench, and a second capacitor electrode having a portion insulatively stacked with said first capacitor electrode in the trench.

摘要翻译： 公开了一种动态随机存取存储器，其包括具有形成在半导体衬底中的晶体管的沟槽型存储单元和布置在形成在衬底中并具有沟槽结构的沟槽中的电容器。 电容器包括形成在衬底上的杂质掺杂半导体层，以围绕沟槽并且具有与衬底的导电类型相反的导电类型，形成在沟槽中的第一电容器电极和具有绝缘层叠的部分的第二电容器电极 所述第一电容器电极在沟槽中。

公开(公告)号：US08884389B2

公开(公告)日：2014-11-11

申请号：US13618780

申请日：2012-09-14

申请人： Masaru Toko ,  Masahiko Nakayama ,  Akihiro Nitayama ,  Tatsuya Kishi ,  Hisanori Aikawa ,  Hiroaki Yoda

发明人： Masaru Toko ,  Masahiko Nakayama ,  Akihiro Nitayama ,  Tatsuya Kishi ,  Hisanori Aikawa ,  Hiroaki Yoda

IPC分类号： H01L27/22 ,  H01L21/8239 ,  H01L43/10 ,  H01L43/12 ,  H01L43/08

CPC分类号： H01L43/08 ,  H01L27/228 ,  H01L43/10 ,  H01L43/12

摘要： According to one embodiment, a magnetoresistive element comprises a first magnetic layer having a magnetization direction invariable and perpendicular to a film surface, a tunnel barrier layer formed on the first magnetic layer, and a second magnetic layer formed on the tunnel barrier layer and having a magnetization direction variable and perpendicular to the film surface. The first magnetic layer includes an interface layer formed on an upper side in contact with a lower portion of the tunnel barrier layer, and a main body layer formed on a lower side and serving as an origin of perpendicular magnetic anisotropy. The interface layer includes a first area provided on an inner side and having magnetization, and a second area provided on an outer side to surround the first area and having magnetization smaller than the magnetization of the first area or no magnetization.

摘要翻译： 根据一个实施例，磁阻元件包括具有不变且垂直于膜表面的磁化方向的第一磁性层，形成在第一磁性层上的隧道势垒层，以及形成在隧道势垒层上的第二磁性层，并且具有 磁化方向可变并垂直于膜表面。 第一磁性层包括形成在与隧道势垒层的下部相接触的上侧的界面层，以及形成在下侧并用作垂直磁各向异性的原点的主体层。 界面层包括设置在内侧并具有磁化的第一区域和设置在外侧以围绕第一区域并且具有小于第一区域的磁化或不具有磁化的磁化的第二区域。

公开(公告)号：US08334551B2

公开(公告)日：2012-12-18

申请号：US13120987

申请日：2009-08-25

申请人： Kiyotaro Itagaki ,  Yoshihisa Iwata ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaru Kito ,  Hideaki Aochi ,  Akihiro Nitayama

发明人： Kiyotaro Itagaki ,  Yoshihisa Iwata ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaru Kito ,  Hideaki Aochi ,  Akihiro Nitayama

IPC分类号： H01L29/792 ,  G11C11/34

CPC分类号： H01L27/1157 ,  G11C5/02 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/30 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/7926

摘要： Each of the memory blocks includes: a first conductive layer expanding in parallel to the substrate over the first area, n layers of the first conductive layers being formed in a lamination direction and shared by the plurality of memory strings; a first semiconductor layer; and an electric charge accumulation layer. The memory strings are arranged with m columns in a second direction for each of the memory blocks. The wiring layers are arranged in the second direction, formed to extend to the vicinity of one end of the first conductive layer in the first direction from one side of the memory block, and connected via contact plugs to the first conductive layers. A relation represented by (Formula 1) is satisfied: (Formula 1) m>=n

摘要翻译： 每个存储块包括：在第一区域上平行于衬底扩展的第一导电层，n个第一导电层的层以层叠方向形成并由多个存储器串共享; 第一半导体层; 和电荷蓄积层。 对于每个存储块，存储器串按第二方向布置有m列。 布线层沿第二方向布置，形成为从存储块的一侧沿第一方向延伸到第一导电层的一端附近，并且经由接触插塞连接到第一导电层。 满足式（1）所示的关系：（式1）m> = n

公开(公告)号：US20110284947A1

公开(公告)日：2011-11-24

申请号：US13198359

申请日：2011-08-04

申请人： Masaru KITO ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

发明人： Masaru KITO ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

IPC分类号： H01L29/792

CPC分类号： H01L27/11582 ,  G11C16/0483 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578

摘要： A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

摘要翻译： 提供了具有新结构的非易失性半导体存储器件，其中以三维状态层叠存储单元，从而可以减小芯片面积。 本发明的非易失性半导体存储装置是具有串联连接有多个电可编程存储单元的多个存储串的非易失性半导体存储装置。 存储器串包括柱形半导体; 形成在柱状半导体周围的第一绝缘膜; 形成在所述第一绝缘膜周围的电荷存储层; 形成在电荷存储层周围的第二绝缘膜; 并且形成在第二绝缘膜周围的第一或第n电极（n是大于1的自然数）。 存储器串的第一或第n电极和存储器串的其它第一或第n电极分别是以二维状态扩展的第一或第n导体层。

公开(公告)号：US07936004B2

公开(公告)日：2011-05-03

申请号：US11654551

申请日：2007-01-18

申请人： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

发明人： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

IPC分类号： H01L27/115

CPC分类号： H01L27/11582 ,  G11C16/0483 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578

摘要： A nonvolatile semiconductor memory device includes a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; a second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory string and the first to nth electrodes of at least two other memory strings which are adjacent to the memory string in two directions are shared as first to nth conductor layers spread in two dimensions.

摘要翻译： 非易失性半导体存储器件包括其中多个可电可编程存储器单元串联连接的多个存储器串。 存储器串包括柱形半导体; 形成在柱状半导体周围的第一绝缘膜; 形成在所述第一绝缘膜周围的电荷存储层; 形成在电荷存储层周围的第二绝缘膜; 并且形成在第二绝缘膜周围的第一或第n电极（n是大于1的自然数）。 存储器串的第一或第n电极以及在两个方向上与存储器串相邻的至少两个其它存储器串的第一至第n电极被共享为在二维上扩展的第一至第n导体层。

公开(公告)号：US07706175B2

公开(公告)日：2010-04-27

申请号：US11839265

申请日：2007-08-15

申请人： Keiji Hosotani ,  Yoshiaki Asao ,  Akihiro Nitayama

发明人： Keiji Hosotani ,  Yoshiaki Asao ,  Akihiro Nitayama

IPC分类号： G11C11/00

CPC分类号： H01L27/228 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

摘要： A magnetic random access memory includes a first wiring, a second wiring formed above and spaced apart from the first wiring, a magnetoresistive effect element formed between the first wiring and the second wiring, formed in contact with an upper surface of the first wiring, and having a fixed layer, a recording layer, and a nonmagnetic layer formed between the fixed layer and the recording layer, a metal layer formed on the magnetoresistive effect element and integrated with the magnetoresistive effect element to form stacked layers, a first side insulating film formed on side surfaces of the metal layer, the magnetoresistive effect element, and the first wiring, a first contact formed in contact with a side surface of the first side insulating film, and a third wiring formed on the metal layer and the first contact to electrically connect the magnetoresistive effect element and the first contact.

摘要翻译： 磁性随机存取存储器包括第一布线，形成在第一布线上方并与第一布线间隔开的第二布线;形成在与第一布线的上表面接触形成的第一布线和第二布线之间的磁阻效应元件，以及 具有形成在固定层和记录层之间的固定层，记录层和非磁性层，形成在磁阻效应元件上并与磁阻效应元件集成以形成堆叠层的金属层，形成第一侧绝缘膜 在金属层的侧表面，磁阻效应元件和第一布线，与第一侧绝缘膜的侧表面接触形成的第一触点和形成在金属层上的第三布线和第一触点电连接 连接磁阻效应元件和第一触点。