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    Method for dual damascene process using electron beam and ion implantation cure methods for low dielectric constant materials
    31.
    发明授权
    Method for dual damascene process using electron beam and ion implantation cure methods for low dielectric constant materials 有权
    使用电子束的双镶嵌工艺和低介电常数材料的离子注入固化方法

    公开(公告)号：US06271127B1

    公开(公告)日：2001-08-07

    申请号：US09329569

    申请日：1999-06-10

    Applicant: Qizhi Liu ,  David Feiler ,  Bin Zhao ,  Maureen R. Brongo

    Inventor： Qizhi Liu ,  David Feiler ,  Bin Zhao ,  Maureen R. Brongo

    IPC: H01L214763

    CPC classification number: H01L21/76829 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76825 ,  Y10S438/949

    Abstract: Method for dual damascene metallization of semiconductor workpieces which uses a process for creating an etch stop in an insulator thereby eliminating the need for deposition of an etch stop layer. Electron beam exposure is used to cure the insulator, or material having a low dielectric constant. Application of the electron beam to the low dielectric constant material converts the topmost layer of the low dielectric constant material to an etch stop layer, while rapid thermal heating cures the remainder of the low dielectric constant material. Creation of an etch stop layer in the low dielectric constant material can also be achieved by curing the low dielectric constant material using ion implantation.

    Abstract translation: 用于半导体工件的双镶嵌金属化的方法，其使用在绝缘体中产生蚀刻停止的工艺，从而消除了沉积蚀刻停止层的需要。 使用电子束曝光来固化绝缘体或具有低介电常数的材料。 将电子束应用于低介电常数材料将低介电常数材料的最上层转化为蚀刻停止层，同时快速热加热固化低介电常数材料的其余部分。 在低介电常数材料中形成蚀刻停止层也可以通过使用离子注入固化低介电常数材料来实现。

    IC interconnect structures and methods for making same
    32.
    发明授权
    IC interconnect structures and methods for making same 有权
    IC互连结构及其制造方法

    公开(公告)号：US06245663B1

    公开(公告)日：2001-06-12

    申请号：US09163967

    申请日：1998-09-30

    Applicant: Bin Zhao ,  Maureen R. Brongo

    Inventor： Bin Zhao ,  Maureen R. Brongo

    IPC: H01L214763

    CPC classification number: H01L21/76834 ,  H01L21/76807 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods and structures are disclosed for advanced interconnects in sub-micron and sub-half-micron integrated circuit devices fabricated using a single damascene process. a dielectric etch-stop layer (e.g., silicon nitride) is deposited subsequent to rather than prior to CMP processing of the previous metallization layer (e.g., the conductive plug). This scheme effectively eliminates the effect of CMP-induced erosion on the etch-stop layer and therefore allows an extremely thin etch stop to be used. Moreover, a high etch-selectivity can be obtained for the trench etch, and all etch-stop material is removed from beneath the interconnect metal, thereby reducing parasitic effects. A patterned dielectric layer is used as a metal cap in place of the standard blanket silicon nitride layer, thus preventing the formation of blisters and bubbles associated with trapped moisture and gasses, and reducing interconnect capacitance.

    Abstract translation: 公开了使用单个镶嵌工艺制造的亚微米级和次级半微米集成电路器件中的高级互连的方法和结构。 在先前的金属化层（例如，导电插头）的CMP处理之前而不是之前沉积介电蚀刻停止层（例如，氮化硅）。 该方案有效地消除了CMP腐蚀对蚀刻停止层的影响，因此允许使用极薄的蚀刻停止。 此外，可以获得沟槽蚀刻的高蚀刻选择性，并且从互连金属下方去除所有蚀刻停止材料，从而减少寄生效应。 图案化的介电层用作代替标准覆盖氮化硅层的金属盖，从而防止与被捕获的湿气和气体相关联的起泡和气泡的形成，并减少互连电容。

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