公开(公告)号：US07817007B2

公开(公告)日：2010-10-19

申请号：US12194935

申请日：2008-08-20

Applicant: Byoung Hwa Lee ,  Sung Kwon Wi ,  Hyeog Soo Shin ,  Dong Seok Park ,  Sang Soo Park ,  Min Cheol Park

Inventor： Byoung Hwa Lee ,  Sung Kwon Wi ,  Hyeog Soo Shin ,  Dong Seok Park ,  Sang Soo Park ,  Min Cheol Park

IPC: H01F5/00

CPC classification number: H01F17/0013 ,  H01F3/14 ,  H01F17/04

Abstract: There is provided a laminated inductor including: a body where a plurality of magnetic layers are laminated; a coil part formed on the magnetic layers, the coil part including a plurality of conductor patterns and a plurality of conductive vias; first and second external electrodes formed on an outer surface of the body to connect to both ends of the coil part, respectively; and a non-magnetic conductor formed on at least one of the magnetic layers so as to relax magnetic saturation caused by direct current flowing through the coil part. The laminated inductor employs the non-magnetic conductor as a non-magnetic gap to be simplified in a manufacturing process and effectively improved in DC superposition characteristics.

Abstract translation: 提供一种层叠电感器，包括：层叠有多个磁性层的主体; 形成在所述磁性层上的线圈部分，所述线圈部分包括多个导体图案和多个导电通孔; 第一外部电极和第二外部电极分别形成在主体的外表面上以连接到线圈部分的两端; 以及形成在至少一个磁性层上的非磁性导体，以便缓和由直流电流流过线圈部分的磁饱和。 层叠电感器在制造工艺中使用非磁性导体作为非磁性间隙进行简化，并有效地改善了DC叠加特性。

公开(公告)号：US20100254070A1

公开(公告)日：2010-10-07

申请号：US12817046

申请日：2010-06-16

Applicant: Byoung Hwa Lee ,  Sung Kwon Wi ,  Hae Suk Chung ,  Dong Seok Park ,  Sang Soo Park ,  Min Cheol Park

Inventor： Byoung Hwa Lee ,  Sung Kwon Wi ,  Hae Suk Chung ,  Dong Seok Park ,  Sang Soo Park ,  Min Cheol Park

IPC: H01G4/228

CPC classification number: H01G4/30 ,  H01G4/012 ,  H01G4/232

Abstract: A multilayer chip capacitor includes: a capacitor body having first and second side surfaces and a bottom surface; a plurality of first and second internal electrodes in the capacitor body; first and second external electrodes having a first polarity and formed on the first and second side surfaces, respectively, to cover a respective lower edge of the side surfaces and to partially extend to the bottom surface; and a third external electrode having a second polarity and formed on the bottom surface. The internal electrodes are disposed in perpendicular to the bottom surface. Each of the first internal electrodes has a first lead drawn to the first side and bottom surfaces and a second lead drawn to the second side and bottom surfaces. Each of the second internal electrodes has a third lead drawn to the bottom surface.

Abstract translation: 一种多层片状电容器包括：具有第一和第二侧表面和底表面的电容器本体; 电容器主体中的多个第一和第二内部电极; 第一和第二外部电极分别具有第一极性并形成在第一和第二侧表面上，以覆盖侧表面的相应下边缘并部分地延伸到底面; 和具有第二极性并形成在底面上的第三外部电极。 内部电极垂直于底面设置。 每个第一内部电极具有被引导到第一侧面和底部表面的第一引线和被引导到第二侧面和底部表面的第二引线。 每个第二内部电极具有被引导到底面的第三引线。

公开(公告)号：US07630208B2

公开(公告)日：2009-12-08

申请号：US12198342

申请日：2008-08-26

Applicant: Byoung Hwa Lee ,  Sung Kwon Wi ,  Hae Suk Chung ,  Dong Seok Park ,  Sang Soo Park ,  Min Cheol Park

Inventor： Byoung Hwa Lee ,  Sung Kwon Wi ,  Hae Suk Chung ,  Dong Seok Park ,  Sang Soo Park ,  Min Cheol Park

IPC: H05K1/16

CPC classification number: H01G4/232 ,  H01G4/012 ,  H01G4/30 ,  H01G4/385 ,  H05K1/0231 ,  H05K1/113 ,  H05K2201/09309 ,  H05K2201/09772 ,  H05K2201/0979 ,  H05K2201/10015 ,  H05K2201/10636 ,  Y02P70/611

Abstract: Provided is a multilayer chip capacitor including a capacitor body having first and second capacitor units arranged in a lamination direction; and a plurality of external electrodes formed outside the capacitor body. The first capacitor unit includes at least one pair of first and second internal electrodes disposed alternately in an inner part of the capacitor body, the second capacitor unit includes a plurality of third and fourth internal electrodes disposed alternately in an inner part of the capacitor body, and the first to fourth internal electrodes are coupled to the first to fourth external electrodes. The first capacitor unit has a lower equivalent series inductance (ESL) than the second capacitor unit, and the first capacitor unit has a higher equivalent series resistance (ESR) than the second capacitor unit.

Abstract translation: 本发明提供一种多层片状电容器，其包括具有层叠方向配置的第一和第二电容器单元的电容器体; 以及形成在电容器主体外部的多个外部电极。 第一电容器单元包括交替设置在电容器主体的内部的至少一对第一和第二内部电极，第二电容器单元包括交替设置在电容器主体内部的多个第三和第四内部电极， 并且第一至第四内部电极耦合到第一至第四外部电极。 第一电容器单元具有比第二电容器单元更低的等效串联电感（ESL），并且第一电容器单元具有比第二电容器单元更高的等效串联电阻（ESR）。

公开(公告)号：US20080158773A1

公开(公告)日：2008-07-03

申请号：US11979875

申请日：2007-11-09

Applicant: Byoung Hwa Lee ,  Sung Kwon Wi ,  Hae Suk Chung ,  Dong Seok Park ,  Sang Soo Park ,  Min Cheol Park

Inventor： Byoung Hwa Lee ,  Sung Kwon Wi ,  Hae Suk Chung ,  Dong Seok Park ,  Sang Soo Park ,  Min Cheol Park

IPC: H01G4/228 ,  H01G4/005

CPC classification number: H01G4/232 ,  H01G4/005 ,  H01G4/30 ,  H03H2001/0014

Abstract: A multilayer capacitor array having a plurality of multilayer capacitor devices formed in a single multilayer structure, the multilayer capacitor array including: a capacitor body formed by depositing a plurality of dielectric layers and having first and second side surfaces opposite to each other; a plurality of first polarity internal electrodes and second polarity internal electrodes, disposed oppositely to each other in the capacitor body, interposing the dielectric layer there between, and formed of a single electrode plate comprising a single lead, respectively; and a plurality of first polarity external electrodes and second polarity external electrodes, formed on the first side surface and second side surface, respectively, and connected to a correspondent polarity internal electrode via the lead, the first polarity external electrode formed on the first side surface and the second polarity external electrode formed on the second side surface, wherein the numbers of the first polarity external electrodes and the second polarity external electrodes are two or more, respectively, and are identical to each other, and a total number of the multilayer capacitor devices in the multilayer capacitor array is identical to the number of the first polarity external electrodes.

Abstract translation: 1.一种多层电容器阵列，具有形成为单层多层结构的多层多层电容器件，所述层叠电容器阵列包括：通过沉积多个电介质层而形成的电容器体，并且具有彼此相对的第一和第二侧面; 多个第一极性内部电极和第二极性内部电极，其彼此相对设置在电容器主体中，分别在其间插入电介质层，并由单个引线构成的单个电极板形成; 以及多个第一极性外部电极和第二极性外部电极，分别形成在所述第一侧面和所述第二侧面上，并且经由所述引线与相应的极性内部电极连接，所述第一极性外部电极形成在所述第一侧面 和形成在第二侧面上的第二极性外部电极，其中第一极性外部电极和第二极性外部电极的数量分别为两个或更多个，并且彼此相同，并且层叠电容器的总数 多层电容器阵列中的器件与第一极性外部电极的数量相同。

公开(公告)号：US07183872B2

公开(公告)日：2007-02-27

申请号：US11065232

申请日：2005-02-24

Applicant: Byoung Hwa Lee ,  Dong Seok Park ,  Min Cheol Park ,  Sang Soo Park

Inventor： Byoung Hwa Lee ,  Dong Seok Park ,  Min Cheol Park ,  Sang Soo Park

IPC: H03H7/42 ,  H01F5/00

CPC classification number: H01P5/10

Abstract: A laminated balun transformer subminiaturized with a transmission line length reduced below λ/4 without any variation of characteristics. The laminated balun transformer includes a first strip line having one end inputted to a unbalanced signal; a second strip line having connected to the first strip line; a third strip line formed in parallel with the first strip line and connected to a ground and connected to the external electrode for a first balanced signal; a fourth strip line formed in parallel with the second strip line and connected to the external electrode for a ground and the external electrode for a second balanced signal; and a capacitance forming electrode formed in parallel with a portion of the opened end of the second strip line and connected to the external electrode for the unbalanced signal.

Abstract translation: 传输线长度小于λ/ 4的小型化的不平衡 - 不平衡转换变压器，没有任何特性变化。 叠层平衡不平衡变压器包括：一端输入不平衡信号的第一带状线; 连接到第一带状线的第二带状线; 第三带状线，与第一带状线平行地形成并连接到接地并连接到外部电极用于第一平衡信号; 第四带状线，与第二条带线平行地形成并连接到用于接地的外部电极和用于第二平衡信号的外部电极; 以及电容形成电极，其与所述第二带状线的开放端部的一部分平行地形成，并且与所述不平衡信号的外部电极连接。

公开(公告)号：US08681475B2

公开(公告)日：2014-03-25

申请号：US13590270

申请日：2012-08-21

Applicant: Young Ghyu Ahn ,  Byoung Hwa Lee ,  Min Cheol Park ,  Sang Soo Park ,  Dong Seok Park

Inventor： Young Ghyu Ahn ,  Byoung Hwa Lee ,  Min Cheol Park ,  Sang Soo Park ,  Dong Seok Park

IPC: H01G4/06

CPC classification number: H01G4/12 ,  H01G4/228 ,  H01G4/30

Abstract: Disclosed herein is a mounting structure of a circuit board having a multi-layered ceramic capacitor thereon, the multi-layered ceramic capacitor including dielectric sheets laminated thereon and external terminal electrodes formed at both ends thereof, the dielectric sheets having internal electrodes formed thereon, and the external terminal electrodes being connected in parallel with the internal electrode, wherein the internal electrodes are disposed to be in parallel with the circuit board, the external terminal electrodes are bonded to lands of the circuit board by a conductive material, and a bonding height (Ts) of the conductive material is lower than a sum of a gap (Ta) between the circuit board and a bottom surface of the multi-layered ceramic capacitor and a thickness (Tc) of a cover layer on a lower portion of the multi-layered ceramic capacitor, whereby vibration noise can be greatly reduced.

Abstract translation: 这里公开了一种其上具有多层陶瓷电容器的电路板的安装结构，其中层叠有电介质片的多层陶瓷电容器和形成在其两端的外部端子电极，其上形成有内部电极的电介质片，以及 外部端子电极与内部电极并联连接，其中内部电极被设置为与电路板平行，外部端子电极通过导电材料接合到电路板的焊盘，并且接合高度 Ts）低于多层陶瓷电容器的电路板和底面之间的间隙（Ta）和多层陶瓷电容器的下表面的覆盖层的厚度（Tc）之和， 层状陶瓷电容器，从而可以大大降低振动噪声。

公开(公告)号：US08451580B2

公开(公告)日：2013-05-28

申请号：US13286871

申请日：2011-11-01

Applicant: Hae Suk Chung ,  Byoung Hwa Lee ,  Eun Hyuk Chae ,  Eun Hye Choi ,  Kang Heon Hur ,  Dae Bok Oh

Inventor： Hae Suk Chung ,  Byoung Hwa Lee ,  Eun Hyuk Chae ,  Eun Hye Choi ,  Kang Heon Hur ,  Dae Bok Oh

IPC: H01G4/005 ,  H01G4/06

CPC classification number: H01G4/232 ,  H01G4/012 ,  H01G4/12 ,  H01G4/30

Abstract: There is provided a multilayer ceramic capacitor capable of controlling equivalent series resistance (ESR) characteristics. The multilayer ceramic capacitor includes: a ceramic laminate including dielectric layers and a plurality of internal electrodes having different polarities and alternately stacked between the dielectric layers; and external electrodes formed on both sides of the ceramic laminate, wherein each of the internal electrodes includes a main electrode and a lead for connecting the main electrode to the external electrode, and an equivalent series resistance (ESR) value is determined by adjusting a ratio of a width to a length of the lead, whereby the ESR characteristics of the multilayer ceramic capacitor may be controlled.

Abstract translation: 提供了能够控制等效串联电阻（ESR）特性的多层陶瓷电容器。 所述多层陶瓷电容器包括：陶瓷层叠体，其包含电介质层和具有不同极性的多个内部电极，并交替堆叠在所述电介质层之间; 以及形成在陶瓷层叠体两侧的外部电极，其中每个内部电极包括主电极和用于将主电极连接到外部电极的引线，并且通过调节比例来确定等效串联电阻（ESR）值 宽度到引线的长度，由此可以控制多层陶瓷电容器的ESR特性。

公开(公告)号：US08385048B2

公开(公告)日：2013-02-26

申请号：US13529766

申请日：2012-06-21

Applicant: Young Ghyu Ahn ,  Byoung Hwa Lee ,  Min Cheol Park ,  Young Hoon Song ,  Mi Hee Lee

Inventor： Young Ghyu Ahn ,  Byoung Hwa Lee ,  Min Cheol Park ,  Young Hoon Song ,  Mi Hee Lee

IPC: H01G4/06

CPC classification number: H01G4/01 ,  H01G4/12 ,  H01G4/232 ,  H01G4/30

Abstract: There is provided a chip type laminated capacitor, including: a ceramic body including a dielectric layer having a thickness equal to 10 or more times an average particle diameter of a grain included therein and being 3 □m or less; first and second outer electrodes formed on both ends of the ceramic body in a length direction; first and second band parts formed to extend inwardly of the ceramic body in the length direction on a length-width (L-W) plane from the first and second outer electrodes and having different lengths; and third and fourth band parts formed to extend inwardly of the ceramic body in the length direction on a length-thickness (L-T) plane from the first and second outer electrodes and having different lengths.

Abstract translation: 提供了一种片式叠层电容器，其包括：陶瓷体，其包括厚度等于其中包含的晶粒的平均粒径的10倍以上且为3μm以下的电介质层; 第一外电极和第二外电极，其在长度方向上形成在陶瓷体的两端; 第一和第二带部分形成为在第一和第二外部电极的长度（L-W）平面上沿长度方向在陶瓷体的内部延伸并具有不同的长度; 以及第三和第四带部分，其形成为在长度方向上在距第一和第二外部电极的长度 - 厚度（L-T）平面上延伸到陶瓷体的内侧并具有不同的长度。

公开(公告)号：US20120298407A1

公开(公告)日：2012-11-29

申请号：US13481348

申请日：2012-05-25

Applicant: Young Ghyu AHN ,  Byoung Hwa Lee ,  Min Cheol Park ,  Sang Soo Park ,  Dong Seok Park

Inventor： Young Ghyu AHN ,  Byoung Hwa Lee ,  Min Cheol Park ,  Sang Soo Park ,  Dong Seok Park

IPC: H05K1/16

CPC classification number: H05K1/111 ,  H01G4/12 ,  H01G4/30 ,  H05K3/3442 ,  H05K2201/10015 ,  H05K2201/2045 ,  Y02P70/611 ,  Y02P70/613

Abstract: Disclosed herein is a mounting structure of a circuit board having a multi-layered ceramic capacitor thereon. The mounting structure of a circuit board having a multi-layered ceramic capacitor thereon, in which a dielectric layer on which inner electrodes are disposed is stacked and external electrode terminals connecting the inner electrodes in parallel are disposed on both ends thereof, wherein the inner electrodes of the multi-layered ceramic capacitor and the circuit board are disposed so as to be a horizontal direction to connect the external electrode terminals with a land on the circuit board by a conductive material and a ratio of a bonding area ASOLEDER of the conductive material to the area AMLCC of the external electrode terminals AMLCC is set to be less than 1.4, thereby remarkably reducing the vibration noise.

Abstract translation: 这里公开了一种其上具有多层陶瓷电容器的电路板的安装结构。 其上设置有多层陶瓷电容器的电路板的安装结构，其中布置有内部电极的电介质层，并且将其内部电极并联连接的外部电极端子设置在其两端，其中内部电极 将多层陶瓷电容器和电路板设置成水平方向，以通过导电材料将导电材料的外部电极端子与电路板上的焊盘接合，并且将导电材料的接合面积ASOLEDER与 外部电极端子AMLCC的面积AMLCC被设定为小于1.4，从而显着地降低了振动噪声。

公开(公告)号：US20120268860A1

公开(公告)日：2012-10-25

申请号：US13286871

申请日：2011-11-01

Applicant: Hae Suk CHUNG ,  Byoung Hwa Lee ,  Eun Hyuk Chae ,  Eun Hye Choi ,  Kang Heon Hur ,  Dae Bok Oh

Inventor： Hae Suk CHUNG ,  Byoung Hwa Lee ,  Eun Hyuk Chae ,  Eun Hye Choi ,  Kang Heon Hur ,  Dae Bok Oh

IPC: H01G4/30

CPC classification number: H01G4/232 ,  H01G4/012 ,  H01G4/12 ,  H01G4/30

Abstract: There is provided a multilayer ceramic capacitor capable of controlling equivalent series resistance (ESR) characteristics. The multilayer ceramic capacitor includes: a ceramic laminate including dielectric layers and a plurality of internal electrodes having different polarities and alternately stacked between the dielectric layers; and external electrodes formed on both sides of the ceramic laminate, wherein each of the internal electrodes includes a main electrode and a lead for connecting the main electrode to the external electrode, and an equivalent series resistance (ESR) value is determined by adjusting a ratio of a width to a length of the lead, whereby the ESR characteristics of the multilayer ceramic capacitor may be controlled.

Abstract translation: 提供了能够控制等效串联电阻（ESR）特性的多层陶瓷电容器。 所述多层陶瓷电容器包括：陶瓷层叠体，其包含电介质层和具有不同极性的多个内部电极，并交替堆叠在所述电介质层之间; 以及形成在陶瓷层叠体两侧的外部电极，其中每个内部电极包括主电极和用于将主电极连接到外部电极的引线，并且通过调节比例来确定等效串联电阻（ESR）值 宽度到引线的长度，由此可以控制多层陶瓷电容器的ESR特性。