公开(公告)号：US20070160113A1

公开(公告)日：2007-07-12

申请号：US11566658

申请日：2006-12-04

申请人： Chan-Kyung KIM ,  Young-Hyun JUN

发明人： Chan-Kyung KIM ,  Young-Hyun JUN

IPC分类号： G01K7/00

CPC分类号： G01K7/32 ,  G01K7/01 ,  G11C7/04

摘要： Provided are a temperature sensor using a ring oscillator and temperature detection method using the same. One embodiment of the temperature sensor includes a first pulse generator, a second pulse generator, and a counter. The first pulse generator includes a first ring oscillator and generates a first clock signal having a variable period according to a change in temperature. The second pulse generator includes a second ring oscillator and generates a second clock signal having a fixed period. The counter counts a pulse width of the first clock signal as a function of a pulse width of the second clock signal and generates a temperature code.

摘要翻译： 提供了使用环形振荡器的温度传感器和使用其的温度检测方法。 温度传感器的一个实施例包括第一脉冲发生器，第二脉冲发生器和计数器。 第一脉冲发生器包括第一环形振荡器，并根据温度变化产生具有可变周期的第一时钟信号。 第二脉冲发生器包括第二环形振荡器并产生具有固定周期的第二时钟信号。 计数器根据第二时钟信号的脉冲宽度对第一时钟信号的脉冲宽度进行计数，并产生温度代码。

公开(公告)号：US07143303B2

公开(公告)日：2006-11-28

申请号：US10804530

申请日：2004-03-19

申请人： Young-Soo Sohn ,  Chan-Kyung Kim

发明人： Young-Soo Sohn ,  Chan-Kyung Kim

IPC分类号： G06F1/04

CPC分类号： G11C29/028 ,  G06F1/10 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C29/02 ,  G11C29/50012

摘要： The present invention comprises a memory device for compensating for a clock skew that generates a centering error, and a method of compensating for the clock skew. To compensate for a clock skew that causes a centering error between an external clock signal and an output data signal, the memory device includes a phase detector (PD) and an up-down counter. The PD detects a phase difference between the output data signal and the external clock signal and generates an up signal or a down signal depending on the detected phase difference. The up-down counter is enabled by a calibration signal that directs a compensation of the skew and generates an offset code in response to the up signal or the down signal. The offset code is fed back to a delay locked loop (DLL) circuit and aligns the middle points of the output data signal with the edges of the external clock signal.

摘要翻译： 本发明包括用于补偿产生定心误差的时钟偏差的存储器件以及补偿时钟偏移的方法。 为了补偿引起外部时钟信号和输出数据信号之间的定心误差的时钟偏移，存储器件包括相位检测器（PD）和升降计数器。 PD检测输出数据信号和外部时钟信号之间的相位差，并根据检测到的相位差产生上行信号或下降信号。 升降计数器通过校准信号启用，该校准信号指导偏斜的补偿，并响应于向上信号或下降信号产生偏移代码。 偏移码反馈到延迟锁定环路（DLL）电路，并将输出数据信号的中点与外部时钟信号的边沿对齐。

公开(公告)号：US07078955B2

公开(公告)日：2006-07-18

申请号：US10884684

申请日：2004-07-02

申请人： Kwang-hyun Kim ,  Chan-Kyung Kim

发明人： Kwang-hyun Kim ,  Chan-Kyung Kim

IPC分类号： H01L35/00

CPC分类号： G01K7/01 ,  H03K2017/0806

摘要： A temperature sensing circuit and method are provided. An example temperature sensing circuit includes a temperature sensing unit that outputs a temperature signal indicating whether the temperature in the semiconductor device is higher or lower than a reference temperature in response to a first current control signal or a second current control signal by using a first current level that is increased when the temperature rises and a second current level that is reduced when the temperature rises. The temperature sensing unit also includes a storage unit that stores and outputs the temperature signal, and a controller that changes the first current level or the second current level in response to the temperature signal output from the storage unit and generates the first current control signal or the second current control signal used to control the reference temperature.

摘要翻译： 提供了温度检测电路和方法。 一个示例性温度感测电路包括温度感测单元，其通过使用第一电流输出指示半导体器件中的温度是响应于第一电流控制信号还是第二电流控制信号而高于或低于参考温度的温度信号 当温度升高时增加的电平和当温度升高时降低的第二电流水平。 温度检测单元还包括存储并输出温度信号的存储单元，以及响应于从存储单元输出的温度信号而改变第一电流电平或第二电流电平的控制器，并且产生第一电流控制信号或 用于控制参考温度的第二电流控制信号。

公开(公告)号：US20060071687A1

公开(公告)日：2006-04-06

申请号：US11129469

申请日：2005-05-13

申请人： Chan-Kyung Kim

发明人： Chan-Kyung Kim

IPC分类号： H03K19/0175

CPC分类号： H04L25/0272

摘要： In an output driver circuit and method, a control circuit generates a control signal in response to a current internal data signal. An output driver generates an output data signal in response to the control signal. A pre-emphasis circuit adjusts a current flowing through a node having the control signal generated thereon in response to a previous internal data signal. The pre-emphasis circuit may also adjust the output signal in response to the previous internal data signal.

摘要翻译： 在输出驱动器电路和方法中，控制电路响应于当前的内部数据信号产生控制信号。 输出驱动器响应于控制信号产生输出数据信号。 预加重电路响应于先前的内部数据信号来调节流过具有其上产生的控制信号的节点的电流。 预加重电路还可以响应于先前的内部数据信号来调整输出信号。

公开(公告)号：US06903589B2

公开(公告)日：2005-06-07

申请号：US10752500

申请日：2004-01-08

申请人： Chan-kyung Kim

发明人： Chan-kyung Kim

IPC分类号： G11C7/10 ,  H03K5/12 ,  H03K17/16

CPC分类号： H03K17/166

摘要： The output signal from an output driver is compared with first and second reference voltages. A first comparison output signal is generated which exhibits a voltage transition when the output signal reaches the first reference voltage, and a second comparison output signal is generated which exhibits a voltage transition when the output signal reaches the second reference voltage. First and second pulse widths values are then compared. The first pulse width value corresponds to a time delay difference between the voltage transition of the first comparison output signal and the voltage transition of the second comparison output signal, and the second pulse width value corresponds to a target slew rate of the output signal from the output driver. The slew rate of the output signal is decrease when the first pulse width value is smaller than the second pulse width value, and the slew rate of the output signal is increased when the first pulse width value is larger than the second pulse width value.

摘要翻译： 来自输出驱动器的输出信号与第一和第二参考电压进行比较。 产生第一比较输出信号，其在输出信号达到第一参考电压时呈现电压转变，并且产生第二比较输出信号，当输出信号达到第二参考电压时，产生电压转变。 然后比较第一和第二脉冲宽度值。 第一脉冲宽度值对应于第一比较输出信号的电压转变与第二比较输出信号的电压转变之间的时间延迟差，第二脉冲宽度值对应于来自第一比较输出信号的输出信号的目标转换速率 输出驱动。 当第一脉冲宽度值小于第二脉冲宽度值时，输出信号的转换速率降低，并且当第一脉冲宽度值大于第二脉冲宽度值时，输出信号的转换速率增加。

公开(公告)号：US20180189219A1

公开(公告)日：2018-07-05

申请号：US15677475

申请日：2017-08-15

申请人： Chan-Kyung Kim

发明人： Chan-Kyung Kim

IPC分类号： G06F13/40 ,  G06F13/12 ,  G06F3/00

CPC分类号： G06F13/4095 ,  G06F3/002 ,  G06F13/12

摘要： A method and a memory device therefor for reconfiguring a DQ pad organization of the memory device on-the-fly. A DQ organization reconfiguration control unit generates a control signal for reconfiguring the DQ pad organization into a desired mode based on a user command. A DQ organization reconfiguration unit is provided between P DQ pads and memory cell arrays and reconfigures organization P DQ pads on-the-fly in any one among Xi DQ pad modes, where i=1, 2, 4, 8, 16, 32, 64, and 128, based on the control signal. For the reconfiguration of the organization of the DQ pads, a plurality of bus lines for data transfer, being switchable by a control signal, are provided. The bus lines are implemented utilizing at least one of the M3 and M4 metal layers of the memory device.

公开(公告)号：US20180107406A1

公开(公告)日：2018-04-19

申请号：US15603255

申请日：2017-05-23

申请人： SEONG-IL O ,  Nam Sung KIM ,  Young-Hoon SON ,  Chan-Kyung KIM ,  Ho-Young SONG ,  Jung Ho AHN ,  Sang-Joon HWANG

发明人： SEONG-IL O ,  Nam Sung KIM ,  Young-Hoon SON ,  Chan-Kyung KIM ,  Ho-Young SONG ,  Jung Ho AHN ,  Sang-Joon HWANG

IPC分类号： G06F3/06 ,  G06F13/16

CPC分类号： G06F3/0611 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0683 ,  G06F13/1673

摘要： A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.

公开(公告)号：US09076542B2

公开(公告)日：2015-07-07

申请号：US14077274

申请日：2013-11-12

申请人： Dong Hyun Sohn ,  Chan Kyung Kim ,  Yun Sang Lee

发明人： Dong Hyun Sohn ,  Chan Kyung Kim ,  Yun Sang Lee

IPC分类号： G11C11/00 ,  G11C11/14 ,  G11C11/36 ,  G11C11/16

CPC分类号： G11C11/1697 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693

摘要： A magneto-resistive random access memory (MRAM) including an MRAM cell array having an MRAM cell, and a control and voltage generation unit configured to generate a back bias voltage for the MRAM cell. The control and voltage generation unit including a command decoder configured to generate a decoding signal in response to a command output from a memory controller, and a voltage controller and generator configured to generate the back bias voltage with a magnitude based on the decoding signal and a reset signal output from the memory controller.

摘要翻译： 包括具有MRAM单元的MRAM单元阵列的磁阻随机存取存储器（MRAM）以及被配置为产生MRAM单元的反向偏置电压的控制和电压产生单元。 所述控制和电压产生单元包括命令解码器，其被配置为响应于从存储器控制器输出的命令产生解码信号;以及电压控制器和发生器，其被配置为基于所述解码信号产生具有幅度的所述反向偏置电压，以及 从存储器控制器输出的复位信号。

公开(公告)号：US09042152B2

公开(公告)日：2015-05-26

申请号：US13562871

申请日：2012-07-31

申请人： Chan-kyung Kim ,  Hong-sun Hwang ,  Chul-woo Park ,  Sang-beom Kang ,  Hyung-rok Oh

发明人： Chan-kyung Kim ,  Hong-sun Hwang ,  Chul-woo Park ,  Sang-beom Kang ,  Hyung-rok Oh

IPC分类号： G11C11/00 ,  G11C13/00 ,  G11C11/16 ,  G11C7/06 ,  G11C7/08 ,  G11C7/14 ,  G11C11/56

CPC分类号： G11C13/0033 ,  G11C7/062 ,  G11C7/067 ,  G11C7/08 ,  G11C7/14 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0061 ,  G11C2013/0042 ,  G11C2013/0054

摘要： A non-volatile memory device including a cell array, which includes a plurality of memory cells, and a sense amplification circuit. The sense amplification circuit is configured to receive a data voltage of a memory cell, a first reference voltage and a second reference voltage during a data read operation of the memory cell, generate differential output signals based on a voltage level difference between the data voltage and the first and second reference voltages, and output the differential output signals as data read from the memory cell.

摘要翻译： 包括具有多个存储单元的单元阵列和读出放大电路的非易失性存储器件。 感测放大电路被配置为在存储单元的数据读取操作期间接收存储单元的数据电压，第一参考电压和第二参考电压，基于数据电压和数据电压之间的电压电平差产生差分输出信号 第一和第二参考电压，并将差分输出信号作为从存储单元读取的数据输出。

公开(公告)号：USRE45247E1

公开(公告)日：2014-11-18

申请号：US13405703

申请日：2012-02-27

申请人： Chan-kyung Kim

发明人： Chan-kyung Kim

IPC分类号： H03L7/00

CPC分类号： H03L7/0812 ,  H03K5/133 ,  H03K5/1565

摘要： A duty cycle correction circuit and a delay locked loop (DLL) including the duty cycle correction circuit, are capable of controlling their operation in order to correctly analyze the cause of generation of a duty cycle error when the duty cycle error is generated in the DLL. The duty cycle correction circuit selectively outputs to a DLL core duty cycle offset information for controlling a duty cycle of an internal clock signal synchronized to an external clock signal under the control of a switching control signal. The DLL corrects the duty cycle of a reference clock signal according to the duty cycle offset information, thereby outputting a reference clock signal having a 50% duty cycle.

摘要翻译： 包括占空比校正电路的占空比校正电路和延迟锁定环（DLL）能够控制其工作，以正确地分析当在DLL中产生占空比误差时产生占空比误差的原因 。 占空比校正电路选择性地输出到用于在切换控制信号的控制下控制与外部时钟信号同步的内部时钟信号的占空比的DLL核心占空比偏移信息。 DLL根据占空比偏移信息校正参考时钟信号的占空比，从而输出占空比为50％的参考时钟信号。