公开(公告)号：US20090166768A1

公开(公告)日：2009-07-02

申请号：US12322118

申请日：2009-01-27

Applicant: Wei-Jung Lin ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Shau-Lin Shue

Inventor： Wei-Jung Lin ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Shau-Lin Shue

IPC: H01L29/78

CPC classification number: H01L21/28097 ,  H01L29/4975 ,  H01L29/517

Abstract: A fully silicided gate with a selectable work function includes a gate dielectric over the substrate, a first metal silicide layer over the gate dielectric, and a second metal silicide layer wherein the first metal silicide has a different phase then the second metal silicide layer. The metal silicide layers comprises at least one alloy element. The concentration of the alloy element on the interface between the gate dielectric and the metal silicide layers influence the work function of the gate.

Abstract translation: 具有可选择功函数的完全硅化栅包括在衬底上的栅极电介质，栅极电介质上的第一金属硅化物层和第二金属硅化物层，其中第一金属硅化物具有与第二金属硅化物层不同的相。 金属硅化物层包括至少一种合金元素。 栅极电介质和金属硅化物层之间的界面上的合金元素的浓度影响栅极的功函数。

公开(公告)号：US20080122018A1

公开(公告)日：2008-05-29

申请号：US11458503

申请日：2006-07-19

Applicant: Wei-Jung Lin ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Shau-Lin Shue

Inventor： Wei-Jung Lin ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Shau-Lin Shue

IPC: H01L29/78 ,  H01L21/28

CPC classification number: H01L21/28097 ,  H01L29/4975 ,  H01L29/517

Abstract: A fully silicided gate with a selectable work function includes; a gate dielectric over the substrate; and a first metal silicide layer over the gate dielectric, and a second metal silicide layer wherein the first metal silicide has a different phase then the second metal silicide layer. The metal silicide layers comprises at least one alloy element. The concentration of the alloy element on the interface between the gate dielectric and the metal silicide layers influence the work function of the gate.

Abstract translation: 具有可选工作功能的完全硅化栅包括： 衬底上的栅极电介质; 以及在所述栅极电介质上的第一金属硅化物层，以及第二金属硅化物层，其中所述第一金属硅化物具有与所述第二金属硅化物层不同的相。 金属硅化物层包括至少一种合金元素。 栅极电介质和金属硅化物层之间的界面上的合金元素的浓度影响栅极的功函数。

公开(公告)号：US20070178696A1

公开(公告)日：2007-08-02

申请号：US11343648

申请日：2006-01-30

Applicant: Chii-Ming Wu ,  Shih-Wei Chou ,  Gin Wang ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Shau-Lin Shue

Inventor： Chii-Ming Wu ,  Shih-Wei Chou ,  Gin Wang ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Shau-Lin Shue

IPC: H01L21/44

CPC classification number: H01L21/28518

Abstract: A method for forming nickel silicide includes degassing a semiconductor substrate that includes a silicon surface. After the degassing operation, the substrate is cooled prior to a metal deposition process, during a metal deposition process, or both. The cooling suppresses the temperature of the substrate to a temperature less than the temperature required for the formation of nickel silicide. Nickel diffusion is minimized during the deposition process. After deposition, an annealing process is used to urge the formation of a uniform silicide film. In various embodiments, the metal film may include a binary phase alloy containing nickel and a further element.

Abstract translation: 一种形成硅化镍的方法包括对包含硅表面的半导体衬底脱气。 在脱气操作之后，在金属沉积工艺，金属沉积工艺期间或两者之间冷却基板。 冷却将基板的温度抑制到低于形成硅化镍所需的温度的温度。 在沉积过程中镍的扩散最小化。 沉积后，使用退火工艺来促使形成均匀的硅化物膜。 在各种实施例中，金属膜可以包括含有镍和另一元素的二元相合金。

公开(公告)号：US20050239287A1

公开(公告)日：2005-10-27

申请号：US10742202

申请日：2003-12-18

Applicant: Mei-Yun Wang ,  Chih-Wei Chang ,  Cheng-Tung Lin ,  Chii-Ming Wu ,  Shau-Lin Shue

Inventor： Mei-Yun Wang ,  Chih-Wei Chang ,  Cheng-Tung Lin ,  Chii-Ming Wu ,  Shau-Lin Shue

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/336

CPC classification number: H01L21/28052 ,  H01L21/28518 ,  H01L29/665

Abstract: A self-aligned silicide method for integrated circuit and semiconductor device fabrication wherein a metal layer is formed over one or more silicon regions of a substrate and a barrier metal layer is formed over the metal layer using a chemical vapor deposition process. The temperature at which the chemical vapor deposition process is performed causes the metal layer to react with the one or more silicon regions of the substrate to form a metal-silicide film over each of the silicon regions.

Abstract translation: 一种用于集成电路和半导体器件制造的自对准硅化物方法，其中在衬底的一个或多个硅区域上形成金属层，并且使用化学气相沉积工艺在金属层上形成阻挡金属层。 进行化学气相沉积工艺的温度导致金属层与衬底的一个或多个硅区域反应，以在每个硅区域上形成金属硅化物膜。

公开(公告)号：US08304841B2

公开(公告)日：2012-11-06

申请号：US12761918

申请日：2010-04-16

Applicant: Jeff J. Xu ,  Cheng-Tung Lin ,  Hsiang-Yi Wang ,  Wen-Chin Lee ,  Betty Hsieh

Inventor： Jeff J. Xu ,  Cheng-Tung Lin ,  Hsiang-Yi Wang ,  Wen-Chin Lee ,  Betty Hsieh

IPC: H01L21/02

CPC classification number: H01L27/092 ,  H01L21/823835 ,  H01L21/823842

Abstract: A gate-last method for forming a metal gate transistor is provided. The method includes forming an opening within a dielectric material over a substrate. A gate dielectric structure is formed within the opening and over the substrate. A work function metallic layer is formed within the opening and over the gate dielectric structure. A silicide structure is formed over the work function metallic layer.

Abstract translation: 提供了用于形成金属栅极晶体管的最后一种方法。 该方法包括在基底上形成电介质材料内的开口。 栅极电介质结构形成在开口内和衬底上。 工作功能金属层形成在开口内和栅介质结构之上。 在功函数金属层上形成硅化物结构。

公开(公告)号：US07977772B2

公开(公告)日：2011-07-12

申请号：US12777937

申请日：2010-05-11

Applicant: Chen-Hua Yu ,  Cheng-Tung Lin ,  Cheng-Hung Chang ,  Hsiang-Yi Wang ,  Chen-Nan Yeh

Inventor： Chen-Hua Yu ,  Cheng-Tung Lin ,  Cheng-Hung Chang ,  Hsiang-Yi Wang ,  Chen-Nan Yeh

IPC: H01L21/4763

CPC classification number: H01L21/823835 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092

Abstract: A semiconductor device and system for a hybrid metal fully silicided (FUSI) gate structure is disclosed. The semiconductor system comprises a PMOS gate structure, the PMOS gate structure including a first high-κ dielectric layer, a P-metal layer, a mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric layer, the P-metal layer and a fully silicided layer formed on the P-metal layer. The semiconductor system further comprises an NMOS gate structure, the NMOS gate structure includes a second high-κ dielectric layer, the fully silicided layer, and the mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric and the fully silicided layer.

Abstract translation: 公开了一种用于混合金属全硅化（FUSI）栅极结构的半导体器件和系统。 所述半导体系统包括PMOS栅极结构，所述PMOS栅极结构包括第一高<！ - SIPO < 介电层，P金属层，中间间隙金属层，其中中间间隙金属层形成在高金属层之间。 电介质层，P金属层和形成在P金属层上的完全硅化物层。 所述半导体系统还包括NMOS栅极结构，所述NMOS栅极结构包括第二高<！ - SIPO < 电介质层，完全硅化物层和中间间隙金属层，其中中间间隙金属层形成在高介电层之间。 电介质和完全硅化物层。

公开(公告)号：US07892961B2

公开(公告)日：2011-02-22

申请号：US11809337

申请日：2007-05-31

Applicant: Chen-Hua Yu ,  Cheng-Tung Lin ,  Liang-Gi Yao

Inventor： Chen-Hua Yu ,  Cheng-Tung Lin ,  Liang-Gi Yao

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/3215 ,  H01L21/336

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/513 ,  H01L29/517

Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a metal-containing layer on the gate dielectric; and forming a composite layer over the metal-containing layer. The step of forming the composite layer includes forming an un-doped silicon layer substantially free from p-type and n-type impurities; and forming a silicon layer adjoining the un-doped silicon layer. The step of forming the silicon layer comprises in-situ doping a first impurity. (or need to be change to: forming a silicon layer first & then forming un-doped silicon layer) The method further includes performing an annealing to diffuse the first impurity in the silicon layer into the un-doped silicon layer.

Abstract translation: 一种形成半导体结构的方法包括提供半导体衬底; 在所述半导体衬底上形成栅介电层; 在所述栅极电介质上形成含金属层; 并在该含金属层上形成复合层。 形成复合层的步骤包括形成基本上不含p型和n型杂质的未掺杂硅层; 以及形成邻近所述未掺杂硅层的硅层。 形成硅层的步骤包括原位掺杂第一杂质。 （或者需要改变为：首先形成硅层，然后形成未掺杂的硅层）。该方法还包括执行退火以将硅层中的第一杂质扩散到未掺杂的硅层中。

公开(公告)号：US20100084718A1

公开(公告)日：2010-04-08

申请号：US12354558

申请日：2009-01-15

Applicant: Chung-Shi LIU ,  Hsiang-Yi WANG ,  Cheng-Tung LIN ,  Chen-Hua YU

Inventor： Chung-Shi LIU ,  Hsiang-Yi WANG ,  Cheng-Tung LIN ,  Chen-Hua YU

IPC: H01L29/78 ,  H01L21/283 ,  H01L21/336

CPC classification number: H01L21/28088 ,  H01L21/265 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/78

Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming a high-k dielectric over a substrate, forming a first metal layer over the high-k dielectric, forming a second metal layer over the first metal layer, forming a first silicon layer over the second metal layer, implanting a plurality of ions into the first silicon layer and the second metal layer overlying a first region of the substrate, forming a second silicon layer over the first silicon layer, patterning a first gate structure over the first region and a second gate structure over a second region, performing an annealing process that causes the second metal layer to react with the first silicon layer to form a silicide layer in the first and second gate structures, respectively, and driving the ions toward an interface of the first metal layer and the high-k dielectric in the first gate structure.

Abstract translation: 本公开提供一种制造半导体器件的方法，其包括在衬底上形成高k电介质，在高k电介质上形成第一金属层，在第一金属层上形成第二金属层，形成第一硅 在所述第二金属层上方，将多个离子注入到所述第一硅层中，并且所述第二金属层覆盖在所述基板的第一区域上，在所述第一硅层上形成第二硅层，在所述第一区上形成第一栅极结构 以及在第二区域上的第二栅极结构，执行使所述第二金属层与所述第一硅层反应以在所述第一和第二栅极结构中分别形成硅化物层的退火处理，并将所述离子驱动到 第一栅极结构中的第一金属层和高k电介质。

公开(公告)号：US07629655B2

公开(公告)日：2009-12-08

申请号：US11688592

申请日：2007-03-20

Applicant: Chen-Hua Yu ,  Cheng-Tung Lin ,  Chen-Nan Yeh

Inventor： Chen-Hua Yu ,  Cheng-Tung Lin ,  Chen-Nan Yeh

IPC: H01L29/78

CPC classification number: H01L21/26506 ,  H01L21/28044 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6653

Abstract: A system and method for forming a semiconductor device with a reduced source/drain extension parasitic resistance is provided. An embodiment comprises implanting two metals (such as ytterbium and nickel for an NMOS transistor or platinum and nickel for a PMOS transistor) into the source/drain extensions after silicide contacts have been formed. An anneal is then performed to create a second silicide region within the source/drain extension. Optionally, a second anneal could be performed on the second silicide region to force a further reaction. This process could be performed to multiple semiconductor devices on the same substrate.

Abstract translation: 提供了一种用于形成具有降低的源极/漏极延伸寄生电阻的半导体器件的系统和方法。 一个实施例包括在形成硅化物接触之后，将两种金属（例如用于NMOS晶体管的镱和镍或用于PMOS晶体管的铂和镍）注入到源极/漏极延伸部中。 然后进行退火以在源极/漏极延伸部内产生第二硅化物区域。 任选地，可以在第二硅化物区域上进行第二退火以迫使进一步的反应。 该过程可以对同一衬底上的多个半导体器件执行。

公开(公告)号：US20090280632A1

公开(公告)日：2009-11-12

申请号：US12118919

申请日：2008-05-12

Applicant: Cheng-Tung Lin ,  Yung-Sheng Chiu ,  Hsiang-Yi Wang ,  Chia-Lin Yu ,  Chen-Hua Yu

Inventor： Cheng-Tung Lin ,  Yung-Sheng Chiu ,  Hsiang-Yi Wang ,  Chia-Lin Yu ,  Chen-Hua Yu

IPC: H01L21/3205

CPC classification number: H01L21/28088 ,  H01L21/28079 ,  H01L21/28185 ,  H01L21/3141 ,  H01L21/823437 ,  H01L21/823828 ,  H01L29/513 ,  H01L29/517

Abstract: MOSFETs having stacked metal gate electrodes and methods of making the same are provided. The MOSFET gate electrode includes a gate metal layer formed atop a high-k gate dielectric layer. The metal gate electrode is formed through a low oxygen content deposition process without charged-ion bombardment to the wafer substrate. Metal gate layer thus formed has low oxygen content and may prevent interfacial oxide layer regrowth. The process of forming the gate metal layer generally avoids plasma damage to the wafer substrate.

Abstract translation: 提供具有层叠金属栅电极的MOSFET及其制造方法。 MOSFET栅电极包括形成在高k栅极电介质层顶上的栅极金属层。 通过低氧含量沉积工艺形成金属栅电极而不对晶片衬底进行带电离子轰击。 如此形成的金属栅极层的氧含量低，并且可以防止界面氧化层再生长。 形成栅极金属层的过程通常避免了对晶片衬底的等离子体损伤。