公开(公告)号：US06653674B2

公开(公告)日：2003-11-25

申请号：US10227124

申请日：2002-08-23

Applicant: Shyue Fong Quek ,  Ting Cheong Ang ,  Sang Yee Loong ,  Puay Ing Ong

Inventor： Shyue Fong Quek ,  Ting Cheong Ang ,  Sang Yee Loong ,  Puay Ing Ong

IPC: H01L2976

CPC classification number: H01L29/66772 ,  H01L21/76264 ,  H01L21/76281 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66636 ,  H01L29/66825 ,  H01L29/78621

Abstract: A semiconductor device is provided having angled dopant implantation and vertical trenches in the silicon on insulator substrate adjacent to the sides of a semiconductor gate. A second dopant implantation is in the exposed the source/drain junctions. Contacts having inwardly curved cross-sectional widths in the semiconductor substrate connect vertically to the exposed source/drain junctions either directly or through salicided contact areas.

公开(公告)号：US06495399B1

公开(公告)日：2002-12-17

申请号：US09431238

申请日：1999-11-01

Applicant: Shyue-Fong Quek ,  Ting Cheong Ang ,  Duay Ing Ong ,  Sang Yee Loong

Inventor： Shyue-Fong Quek ,  Ting Cheong Ang ,  Duay Ing Ong ,  Sang Yee Loong

IPC: H01L2150

CPC classification number: H01L23/3107 ,  H01L23/5221 ,  H01L23/5222 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor chip device package comprised of a semiconductor substrate having semiconductor devices formed on the semiconductor substrate. At least one dielectric layer is over the semiconductor substrate. At least one layer of interconnects is over the semiconductor devices and within the at least one respective dielectric layer with at least a portion of the interconnects being separated by voids having a vacuum or air therein. A passivation layer is over the uppermost of the at least one layer of interconnects. Wherein the semiconductor chip device is vacuum sealed within a semiconductor chip device package.

Abstract translation: 一种半导体芯片器件封装，包括形成在半导体衬底上的具有半导体器件的半导体衬底。 至少一个电介质层在半导体衬底之上。 至少一层互连在半导体器件之上，并且在至少一个相应的电介质层内，其中至少一部分互连由其中具有真空或空气的空隙分开。 钝化层位于至少一层互连层的最上面。 其中半导体芯片器件被真空密封在半导体芯片器件封装内。

公开(公告)号：US06455384B2

公开(公告)日：2002-09-24

申请号：US09972645

申请日：2001-10-09

Applicant: Ting Cheong Ang ,  Shyue Fong Quek ,  Jun Song ,  Xing Yu

Inventor： Ting Cheong Ang ,  Shyue Fong Quek ,  Jun Song ,  Xing Yu

IPC: H01L21336

CPC classification number: H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834

Abstract: A process for fabricating a MOSFET device, featuring source/drain extension regions, formed after the utilization of high temperature processes, such as heavily doped source/drain regions, has been developed. Disposable insulator spacers are formed on the sides of doped, SEG silicon regions, followed formation of a gate insulator layer, and an overlying gate structure, on a region of the semiconductor substrate located between the doped SEG silicon regions. The temperature experienced during these process steps result in the formation of the heavily doped source/drain, underlying the SEG silicon regions. Selective removal of the disposable spacers, allows the source/drain extension regions to be placed in the space vacated by the disposable spacers, adjacent to the heavily doped source/drain region. Insulator spacers are then used to fill the spaces vacated by removal of the disposable spacers, directly overlying the source/drain extension regions. Additional iterations include the use of an L shaped spacer, overlying the source/drain extension region, as well as the formation of metal silicide, on the doped SEG silicon regions, and on the gate structures.

Abstract translation: 已经开发了一种用于制造MOSFET器件的方法，其特征在于在利用高温工艺（例如重掺杂源极/漏极区域）之后形成的源极/漏极延伸区域。 在掺杂的SEG硅区域的侧面上形成一次性绝缘体间隔物，随后在位于掺杂的SEG硅区域之间的半导体衬底的区域上形成栅极绝缘体层和覆盖栅极结构。 在这些工艺步骤中经历的温度导致SEG硅区域下方的重掺杂源极/漏极的形成。 选择性地去除一次性间隔件允许源极/漏极延伸区域被放置在与重掺杂的源极/漏极区域相邻的由一次性间隔物空出的空间中。 然后使用绝缘体间隔物来填充通过去除一次性间隔件而空出的空间，直接覆盖源极/漏极延伸区域。 另外的迭代包括在掺杂的SEG硅区域上以及栅极结构上使用覆盖源极/漏极延伸区域的L形间隔物以及金属硅化物的形成。

公开(公告)号：US06416909B1

公开(公告)日：2002-07-09

申请号：US09618673

申请日：2000-07-18

Applicant: Shyue Fong Quek ,  Ting Cheong Ang ,  Swee Hong Choo ,  Sang Yee Loong

Inventor： Shyue Fong Quek ,  Ting Cheong Ang ,  Swee Hong Choo ,  Sang Yee Loong

IPC: G03F900

CPC classification number: G03F1/30 ,  G03F7/70216

Abstract: A new process for fabricating an alternating phase-shifting photomask having an alignment monitor is described. An opaque layer is provided overlying a substrate. The opaque layer is patterned to provide a mask pattern. A phase-shifting pattern is formed on the substrate wherein a portion of the phase-shifting pattern comprises an alignment monitor whereby alignment between the mask pattern and the phase-shifting pattern can be tested.

Abstract translation: 描述了一种用于制造具有对准监视器的交替移相光掩模的新工艺。 覆盖在衬底上的不透明层被提供。 将不透明层图案化以提供掩模图案。 在基板上形成有一个移相图案，其中一部分移相图案包括对准监视器，从而可以测试掩模图案和移相图案之间的对准。

公开(公告)号：US06329253B1

公开(公告)日：2001-12-11

申请号：US09434922

申请日：1999-11-05

Applicant: Jun Song ,  Yonqzang Zhang ,  Shyue Fong Quek ,  Ting Cheong Ang ,  Jun Cai ,  Puay Ing Ong

Inventor： Jun Song ,  Yonqzang Zhang ,  Shyue Fong Quek ,  Ting Cheong Ang ,  Jun Cai ,  Puay Ing Ong

IPC: H01L21336

CPC classification number: H01L29/66621 ,  H01L21/76224 ,  H01L27/0266 ,  H01L29/7834

Abstract: A method for forming a novel thick oxide electrostatic discharge device using shallow trench isolation technology is described. A trench is etched into a semiconductor substrate. An oxide layer is deposited overlying the semiconductor substrate and filling the trench. The oxide within the trench is partially etched away leaving the oxide on the sidewalls and bottom of the trench. The oxide is polished away to the surface of the semiconductor substrate whereby oxide remains only on the sidewalls and bottom of the trench. A gate is formed within the trench whereby the gate is surrounded by the oxide. First ions are implanted into the semiconductor substrate adjacent to the trench to form N-wells. Second ions are implanted into the semiconductor substrate in a top portion of the N-wells to form source/drain regions. Third ions are implanted into the semiconductor substrate underlying the N-wells and underlying the trench to form electrostatic discharge trigger taps. This completes formation of an electrostatic discharge device in the fabrication of integrated circuits.

Abstract translation: 描述了使用浅沟槽隔离技术形成新的厚氧化物静电放电装置的方法。 将沟槽蚀刻到半导体衬底中。 沉积在半导体衬底上并填充沟槽的氧化物层。 部分地蚀刻沟槽内的氧化物，留下沟槽的侧壁和底部上的氧化物。 氧化物被抛光到半导体衬底的表面，由此氧化物仅保留在沟槽的侧壁和底部上。 在沟槽内形成栅极，由此栅极被氧化物包围。 将第一离子注入到与沟槽相邻的半导体衬底中以形成N阱。 在N阱的顶部将第二离子注入到半导体衬底中以形成源/漏区。 将第三离子注入位于N阱下方并位于沟槽下方的半导体衬底中以形成静电放电触发抽头。 这就形成了集成电路制造中的静电放电装置。

公开(公告)号：US06303414B1

公开(公告)日：2001-10-16

申请号：US09614558

申请日：2000-07-12

Applicant: Ting Cheong Ang ,  Shyue Fong Quek ,  Sang Yee Loong ,  Jun Song

Inventor： Ting Cheong Ang ,  Shyue Fong Quek ,  Sang Yee Loong ,  Jun Song

IPC: H01L2100

CPC classification number: H01L21/84 ,  H01L27/1203

Abstract: An integrated microelectronics semiconductor circuit fabricated on a silicon-on-insulator (SOI) type substrate can be protected from unwanted current surges and excessive heat buildup during fabrication by means of a heat-dissipating, protective plasma-induced-damage (PID) diode. The present invention fabricates such a protective diode as a part of the overall scheme in which the transistor devices are formed.

Abstract translation: 在绝缘体上硅（SOI）型衬底上制造的集成微电子半导体电路可以通过散热，保护等离子体诱导损伤（PID）二极管在制造期间免受不必要的电流浪涌和过度积累热量。 本发明制造这样的保护二极管作为其中形成晶体管器件的整体方案的一部分。

公开(公告)号：US06252290B1

公开(公告)日：2001-06-26

申请号：US09425903

申请日：1999-10-25

Applicant: Shyue Fong Quek ,  Ting Cheong Ang ,  Lap Chan ,  Sang Yee Loong

Inventor： Shyue Fong Quek ,  Ting Cheong Ang ,  Lap Chan ,  Sang Yee Loong

IPC: H01L2900

CPC classification number: H01L21/7682 ,  H01L21/76807 ,  H01L21/76835 ,  H01L2221/1026

Abstract: A method of fabricating a dual damascene interconnect structure in a semiconductor device, comprises the following steps. A first level via photo sensitive dielectric layer is deposited and exposed over a semiconductor structure. A first level trench photo sensitive dielectric layer is deposited and exposed over the first via photo sensitive dielectric layer. The exposed first level via photo sensitive dielectric and trench photo sensitive dielectric layers are patterned and etched to form a first level dual damascene opening. The first level dual damascene opening comprises an integral first level via and metal line openings. A first level metal layer is deposited over the first level trench photo sensitive dielectric layer, filling the first level dual damascene opening. The first level metal layer is planarized to form at least one first level dual damascene interconnect having a first level horizontal metal line and a first level vertical via stack. The above steps are repeated n-1 times to form n-1 more dual damascene interconnects over the first level dual damascene interconnect where n is the number of interconnect levels desired. A passivation layer is deposited and patterned over the nth metal dual damascene interconnect layer to form openings in the passivation layer. The n number of via photo sensitive dielectric and trench photo sensitive dielectric layers are stripped and removed beneath the passivation layer openings and between the plurality of dual damascene structures wherein the portion of the via photo sensitive dielectric underneath the horizontal metal lines of the stripped trench photo sensitive dielectric layers remains.

Abstract translation: 一种在半导体器件中制造双镶嵌互连结构的方法，包括以下步骤。 通过光敏电介质层的第一级沉积并暴露在半导体结构上。 第一级沟槽光电介质层被沉积并暴露在第一通孔光敏介电层上。 通过光敏电介质和沟槽光敏电介质层曝光的第一级被图案化和蚀刻以形成第一级双镶嵌开口。 第一级双镶嵌开口包括集成的第一级通孔和金属线开口。 第一级金属层沉积在第一级沟槽光敏介电层上，填充第一级双镶嵌开口。 第一级金属层被平坦化以形成具有第一级水平金属线和第一级垂直通孔叠层的至少一个第一级双镶嵌互连。 上述步骤重复n-1次，以在第一级双镶嵌互连上形成n-1个双镶嵌互连，其中n是所需的互连级数。 在第n个金属双镶嵌互连层上沉积并图案化钝化层，以在钝化层中形成开口。 在钝化层开口之下和多个双镶嵌结构之间剥离并除去n个通孔光敏电介质层和沟槽光敏介电层，其中通过光敏电介质的部分在剥离的沟槽照片的水平金属线下方 保持敏感的电介质层。

公开(公告)号：US06214680B1

公开(公告)日：2001-04-10

申请号：US09460111

申请日：1999-12-13

Applicant: Shyue Fong Quek ,  Ting Cheong Ang ,  Puay Ink Ong ,  Sang Yee Loong

Inventor： Shyue Fong Quek ,  Ting Cheong Ang ,  Puay Ink Ong ,  Sang Yee Loong

IPC: H01L21336

CPC classification number: H01L29/66492 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545

Abstract: A new method of fabricating a MOSFET device is described. A semiconductor substrate is provided and isolation areas are formed isolating active areas in the substrate. An oxide layer is provided overlying both the substrate and isolation area and is patterned and etched to expose two areas within an isolated active area of the substrate. Selective epitaxial growth (SEG) using intrinsic silicon is performed to fill the exposed substrate areas formed in the previous etch step. The oxide layer region in the active area between the two epitaxially grown silicon regions is then etched, exposing the substrate. This is followed by a gate oxide growth and a polysilicon deposition. Planarization is then performed on the surface to expose the two epitaxially grown silicon regions. A second oxide is grown consuming some of the polysilicon gate and the epitaxially grown silicon. This consumption occurs at a higher rate at the upper surface and thus shapes the gate and epitaxially grown silicon into trapezoids with the base being wider than the top. The oxide is then etched leaving V-shaped trenches between the polysilicon and epitaxially grown silicon. A low-angle implantation is performed creating the source/drain extensions in the substrate below the V-shaped trenches. A third oxide is deposited filling the V-shaped groove and overlying the surface of the wafer. A second planarization is performed exposing the top of the epitaxially grown silicon regions and the polysilicon gate. A second implantation is performed to dope the polysilicon gate and epitaxially grown silicon regions. The doped portions of the epitaxially grown silicon form the source drain electrodes of the MOSFET. This is then followed by a salicidation step for metalization and annealing of the second implantation completing the MOSFET device.

Abstract translation: 描述了一种制造MOSFET器件的新方法。 提供半导体衬底，并且形成隔离区域以隔离衬底中的有源区域。 提供覆盖衬底和隔离区域的氧化物层，并且被图案化和蚀刻以暴露衬底的隔离有效区域内的两个区域。 执行使用本征硅的选择性外延生长（SEG）以填充在先前蚀刻步骤中形成的暴露的衬底区域。 然后蚀刻两个外延生长的硅区域之间的有源区域中的氧化物层区域，暴露衬底。 之后是栅极氧化物生长和多晶硅沉积。 然后在表面上进行平面化以暴露两个外延生长的硅区域。 第二氧化物生长消耗一些多晶硅栅极和外延生长的硅。 这种消耗以较高的速率发生在上表面，因此将浇口和外延生长的硅形成为梯形，基部比顶部宽。 然后蚀刻氧化物，留下多晶硅和外延生长的硅之间的V形沟槽。 执行低角度注入，在V形沟槽下面的衬底中产生源极/漏极延伸部。 沉积填充V形槽并覆盖晶片表面的第三氧化物。 进行外延生长的硅区域和多晶硅栅极的顶部的第二平面化。 进行第二次注入以掺杂多晶硅栅极和外延生长的硅区域。 外延生长硅的掺杂部分形成MOSFET的源极漏极。 然后进行用于金属化和退火完成MOSFET器件的第二次注入的盐析步骤。

公开(公告)号：US6143598A

公开(公告)日：2000-11-07

申请号：US246893

申请日：1999-02-08

Applicant: John Elmslie Martin ,  Lap Chan ,  John Leonard Sudijono ,  Ting Cheong Ang

Inventor： John Elmslie Martin ,  Lap Chan ,  John Leonard Sudijono ,  Ting Cheong Ang

IPC: H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/8242

CPC classification number: H01L28/40 ,  H01L28/60 ,  H01L21/3144 ,  H01L21/31604 ,  H01L27/10852

Abstract: A capacitor element of a semiconductor device used for high density semiconductor circuits is formed by the steps of forming the bottom plate of the capacitor, submitting the top of the bottom plate to plasma treatment in an oxidizing medium where nitrogen and oxygen are present, depositing a dielectric layer and submitting the top of the dielectric layer to plasma treatment in an oxidizing medium where nitrogen and oxygen are present. Various materials are used for the plasma treatment in an oxidizing medium where nitrogen and oxygen are present. While the present invention uses amorphous silicon as the dielectric material, plasma treatment in an oxidizing medium where nitrogen and oxygen are present can readily applied to a number of other dielectric materials. The objective in constructing capacitors for semiconductor circuits is to reduce the thickness of the dielectric material as much as possible and use a dielectric material for the dielectric which has a high dielectric constant, this increases the value of the capacitor electrical charge which can be carried by the capacitor. The objective of the present invention is to eliminate the leakage current between the plates of a capacitor so that the capacitor can maintain a high voltage between the top and the bottom plate.

Abstract translation: 用于高密度半导体电路的半导体器件的电容器元件是通过形成电容器的底板的步骤形成的，将底板的顶部在存在氮和氧的氧化介质中进行等离子体处理， 介电层，并将介电层的顶部在存在氮和氧的氧化介质中进行等离子体处理。 在存在氮和氧的氧化介质中使用各种材料进行等离子体处理。 虽然本发明使用非晶硅作为介电材料，但在存在氮和氧的氧化介质中的等离子体处理可以容易地应用于许多其它电介质材料。 用于半导体电路构造电容器的目的是尽可能地减小电介质材料的厚度，并且使用具有高介电常数的电介质的介电材料，这增加了电容器电荷的值 电容器。 本发明的目的是消除电容器板之间的漏电流，使得电容器能够在顶板和底板之间保持高电压。

公开(公告)号：US06090691A

公开(公告)日：2000-07-18

申请号：US439366

申请日：1999-11-15

Applicant: Ting Cheong Ang ,  Shyue Fong Quek ,  Xing Yu ,  Ying Keung Leung

Inventor： Ting Cheong Ang ,  Shyue Fong Quek ,  Xing Yu ,  Ying Keung Leung

IPC: H01L21/225 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/417 ,  H01L21/22

CPC classification number: H01L29/66492 ,  H01L21/823814 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/66545 ,  H01L21/2255 ,  H01L29/665

Abstract: A method for forming a raised source and drain structure without using selective epitaxial silicon growth. A semiconductor substrate is provided having one or more gate areas covered by dielectric structures. Doped polysilicon structures are adjacent to the dielectric structures on each side and are co-planar with the dielectric structures from a CMP process. The first dielectric structures are removed to form gate openings and a liner oxide layer is formed on the bottom and sidewalls of the gate openings. Dielectric spacers are formed on the liner oxide layer over the sidewalls of the gate openings, and the liner oxide layer is removed from the bottom of the gate openings and from over the doped polysilicon structures. Source and drain regions are formed in the semiconductor substrate by diffusing impurity ions from the doped polysilicon layer. A gate oxide layer and a gate polysilicon layer are formed over the semiconductor structure and the gate polysilicon layer is planarized to form a gate electrode. In a key step, the dielectric spacers are removed to form spacer openings, and impurity ions are implanted through the spacer openings and annealed to form source and drain extensions. The dielectric spacers are reformed and a self-aligned silicide layer is formed on the doped polysilicon structure and the gate electrode. Alternatively, the self-aligned silicide layer can be formed prior to removing the dielectric spacers and implanting ions to form source and drain extensions.

Abstract translation: 一种用于在不使用选择性外延硅生长的情况下形成隆起的源极和漏极结构的方法。 提供具有被介电结构覆盖的一个或多个栅极区域的半导体衬底。 掺杂的多晶硅结构与每一侧上的电介质结构相邻，并且与来自CMP工艺的电介质结构共面。 去除第一电介质结构以形成栅极开口，并且在栅极开口的底部和侧壁上形成衬里氧化物层。 在栅极开口的侧壁上的衬垫氧化物层上形成介质间隔物，并且从栅极开口的底部和掺杂的多晶硅结构上方移除衬里氧化物层。 通过从掺杂多晶硅层扩散杂质离子，在半导体衬底中形成源区和漏区。 在半导体结构上形成栅极氧化物层和栅极多晶硅层，并且平坦化栅极多晶硅层以形成栅电极。 在关键步骤中，去除电介质间隔物以形成间隔开口，并通过间隔开孔注入杂质离子并退火以形成源极和漏极延伸部分。 电介质间隔物被重整，并且在掺杂多晶硅结构和栅电极上形成自对准的硅化物层。 或者，可以在去除电介质间隔物和注入离子以形成源极和漏极延伸部之前形成自对准硅化物层。