公开(公告)号：US20120292763A1

公开(公告)日：2012-11-22

申请号：US13565416

申请日：2012-08-02

申请人： Ronald G. Filippi ,  John A. Fitzsimmons ,  Kevin Kolvenbach ,  Ping-Chuan Wang

发明人： Ronald G. Filippi ,  John A. Fitzsimmons ,  Kevin Kolvenbach ,  Ping-Chuan Wang

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/00 ,  H01L2224/05552

摘要： A through-substrate via (TSV) structure includes at least two electrically conductive via segments embedded in a substrate and separated from each other by an electrically conductive barrier layer therebetween. The length of each individual conductive via segment is typically equal to, or less than, the Blech length of the conductive material so that the stress-induced back flow force, generated by each conductive barrier layer, cancels the electromigration force in each conductive via segment. Consequently, the TSV structures are immune to electromigration, and provide reliable electrical connections among a chips stacked in 3 dimensions.

摘要翻译： 贯穿衬底通孔（TSV）结构包括至少两个嵌入衬底中的导电通路段，并且通过它们之间的导电阻挡层彼此分离。 每个单独的导电通路段的长度通常等于或小于导电材料的漂浮长度，使得由每个导电阻挡层产生的应力引起的后向流动力抵消每个导电通路段中的电迁移力 。 因此，TSV结构免于电迁移，并且在三维堆叠的芯片之间提供可靠的电连接。

公开(公告)号：US08310097B2

公开(公告)日：2012-11-13

申请号：US12770535

申请日：2010-04-29

申请人： Shin-Chuan Wang ,  Jung-Chi Yang ,  Po-Ming Chen ,  Chun-Te Wu

发明人： Shin-Chuan Wang ,  Jung-Chi Yang ,  Po-Ming Chen ,  Chun-Te Wu

IPC分类号： H02J7/00 ,  H02J9/00

CPC分类号： H02J9/06 ,  Y10T307/625 ,  Y10T307/729

摘要： The present invention discloses a temperature-sensing uninterruptible power supply system and a method for controlling the same. The temperature-sensing uninterruptible power supply system comprises a data processing device, an uninterruptible power supply device, a human temperature sensing module, and a monitoring software; the control method comprises the steps of: the human temperature sensing module detecting a human temperature in a specific distance range; the monitoring software determining whether a user leave from the specific distance range; the uninterruptible power supply device switching to a power-saving mode and commanding the data processing device to shot down; the human temperature sensing module detecting that the user is back to the specific distance range; and restarting the uninterruptible power supply device and commanding the data processing device to reboot.

摘要翻译： 本发明公开了一种温度感测不间断电源系统及其控制方法。 温度感测不间断电源系统包括数据处理装置，不间断电源装置，人体感测模块和监视软件; 该控制方法包括以下步骤：人体温度感测模块检测特定距离范围内的人体温度; 所述监视软件确定用户是否离开所述特定距离范围; 不间断电源装置切换到省电模式并命令数据处理装置被击倒; 人体感测模块检测用户是否回到特定距离范围; 并重新启动不间断电源设备并命令数据处理设备重新启动。

公开(公告)号：US20120264289A1

公开(公告)日：2012-10-18

申请号：US13531015

申请日：2012-06-22

申请人： Hanyi Ding ,  Ronald G. Filippi ,  Jong-Ru Guo ,  Ping-Chuan Wang

发明人： Hanyi Ding ,  Ronald G. Filippi ,  Jong-Ru Guo ,  Ping-Chuan Wang

IPC分类号： H01L21/768

CPC分类号： H01L23/528 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.

摘要翻译： 一种集成电路（IC）互连结构，其包括位于电介质中并且在一端耦合到高电流器件的第一通孔和位于电介质中的缓冲金属段，并在其相对端耦合到第一通孔。 缓冲金属段包括在其上形成ILD干酪糖化图案的多个电绝缘介电层（ILD）焊盘以引导电流。 IC互连结构还包括位于介质上的第二通孔，该电介质形成在缓冲金属段上并且在一端耦合到缓冲金属段，并且金属电源线形成在电介质中，并在其相对端耦合到第二通孔。 缓冲金属片段上的ILD焊盘的使用使得能够沿着金属电源线更均匀地分布电流。

公开(公告)号：US20120241977A1

公开(公告)日：2012-09-27

申请号：US13489596

申请日：2012-06-06

申请人： Oleg Gluschenkov ,  Yunsheng Song ,  Tso-Hui Ting ,  Ping-Chuan Wang

发明人： Oleg Gluschenkov ,  Yunsheng Song ,  Tso-Hui Ting ,  Ping-Chuan Wang

IPC分类号： H01L25/00 ,  H01L21/66 ,  H05K13/00 ,  H01L21/60

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L22/20 ,  H01L23/13 ,  H01L23/481 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/1403 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06596 ,  H01L2924/014 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/15311 ,  H05K1/0286 ,  H05K1/142 ,  H05K2201/2018 ,  H05K2203/1572 ,  Y10T29/49117 ,  H01L2924/00

摘要： A modularized interposer includes a plurality of interposer units that are assembled to provide a complete set of electrical connections between two semiconductor chips. At least some of the plurality of interposer units can be replaced with other interposer units having an alternate configuration to enable selection of different functional parts of semiconductor chips to be connected through the modularized interposer. Bonding structures, connected to conductive metal pads located at peripheries of neighboring interposer units and an overlying or underlying portion of a semiconductor chip, can provide electrical connections between the neighboring interposer units. The interposer units can be provided by forming through-substrate vias (TSV's) in a substrate, forming patterned conductive structures on the substrate, and cutting the substrate into interposers.

摘要翻译： 模块化插入器包括多个插入器单元，其被组合以提供两个半导体芯片之间的完整的电连接。 多个插入单元中的至少一些可以被具有替代配置的其它插入单元替代，以便能够通过模块化插入器选择要连接的半导体芯片的不同功能部件。 连接到位于相邻插入单元周围的导电金属焊盘和半导体芯片的上部或下部的结合结构可以在相邻插入单元之间提供电连接。 可以通过在衬底中形成贯穿衬底通孔（TSV）来形成插入器单元，在衬底上形成图案化的导电结构，并将衬底切割成插入层。

公开(公告)号：US20120228580A1

公开(公告)日：2012-09-13

申请号：US13164251

申请日：2011-06-20

申请人： Hsin Chuan Wang ,  Hao Ching Wu

发明人： Hsin Chuan Wang ,  Hao Ching Wu

IPC分类号： H01L33/06 ,  H01L33/14

CPC分类号： H01L27/156 ,  H01L33/145 ,  H01L33/62 ,  H01L2924/0002 ,  H01L2924/00

摘要： A light-emitting diode device and a method for manufacturing the same. In one embodiment, the light-emitting diode device comprises a substrate, an undoped semiconductor layer and a current blocking structure disposed on the substrate in sequence, a plurality of light-emitting structures, separately disposed on the current blocking structure, a plurality of insulating spacers, respectively located between the adjacent light-emitting structures, and a plurality of conductive wires. Each of the light-emitting structures has a first conductivity type semiconductor layer, an active layer, a second conductivity type semiconductor layer, and a first electrode and a second electrode. The first conductivity type semiconductor layer and the second conductivity type semiconductor layer have different conductivity types. The plurality of conductive wires respectively connecting the first electrode of one of the adjacent light-emitting structures and the second electrode of the other light-emitting structure in sequence.

摘要翻译： 发光二极管装置及其制造方法。 在一个实施例中，发光二极管器件依次包括衬底，未掺杂的半导体层和设置在衬底上的电流阻挡结构，分别设置在电流阻挡结构上的多个发光结构，多个绝缘 分别位于相邻的发光结构之间的间隔物和多个导电线。 每个发光结构具有第一导电型半导体层，有源层，第二导电类型半导体层以及第一电极和第二电极。 第一导电类型半导体层和第二导电类型半导体层具有不同的导电类型。 多个导线分别连接相邻的发光结构中的一个的第一电极和另一个发光结构的第二电极。

公开(公告)号：US08259420B2

公开(公告)日：2012-09-04

申请号：US12658005

申请日：2010-02-01

申请人： Tong Zhao ,  Hui Chuan Wang ,  Min Li ,  Kunliang Zhang

发明人： Tong Zhao ,  Hui Chuan Wang ,  Min Li ,  Kunliang Zhang

IPC分类号： G11B5/39 ,  C21D1/04

CPC分类号： G11B5/3906 ,  G01R33/093 ,  G01R33/098 ,  G11B5/3163 ,  G11B2005/3996 ,  H01F10/3254 ,  H01F10/3272 ,  H01F41/303 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  Y10T29/49034 ,  Y10T29/49052

摘要： A composite free layer having a FL1/insertion/FL2 configuration where a top surface of FL1 is treated with a weak plasma etch is disclosed for achieving enhanced dR/R while maintaining low RA, and low λ in TMR or GMR sensors. The weak plasma etch removes less than about 0.2 Angstroms of FL1 and is believed to modify surface structure and possibly increase surface energy. FL1 may be CoFe, CoFe/CoFeB, or alloys thereof with Ni, Ta, Mn, Ti, W, Zr, Hf, Tb, or Nb having a (+) λ value. FL2 may be CoFe, NiFe, or alloys thereof having a (−) λ value. The thin insertion layer includes at least one magnetic element such as Co, Fe, and Ni, and at least one non-magnetic element selected from Ta, Ti, W, Zr, Hf, Nb, Mo, V, Cr, or B. When CoFeBTa is selected as insertion layer, the CoFeB:Ta ratio is from 1:1 to 4:1.

摘要翻译： 公开了具有FL1 /插入/ FL2配置的复合自由层，其中用弱等离子体蚀刻处理FL1的顶表面，以实现增强的dR / R，同时保持低的RA和TMR或GMR传感器中的低λ。 弱等离子体蚀刻去除了小于约0.2埃的FL1，据信可以改变表面结构并可能增加表面能。 FL1可以是具有（+）λ值的Ni，Ta，Mn，Ti，W，Zr，Hf，Tb或Nb的CoFe，CoFe / CoFeB或其合金。 FL2可以是具有（ - ）λ值的CoFe，NiFe或其合金。 薄插入层包括至少一种诸如Co，Fe和Ni的磁性元件和至少一种选自Ta，Ti，W，Zr，Hf，Nb，Mo，V，Cr或B的非磁性元素。 当选择CoFeBTa作为插入层时，CoFeB：Ta的比例为1:1至4:1。

公开(公告)号：US20120212841A1

公开(公告)日：2012-08-23

申请号：US13273210

申请日：2011-10-13

申请人： Kuo-Chuan Wang ,  Yi-Hao Kang ,  Chi-Tang Hsieh ,  Chia-Chang Lee

发明人： Kuo-Chuan Wang ,  Yi-Hao Kang ,  Chi-Tang Hsieh ,  Chia-Chang Lee

IPC分类号： G02B11/16 ,  G02B11/06

CPC分类号： G02B13/16 ,  G02B19/0014 ,  G02B19/0047

摘要： A projection lens for projecting an image beam is provided. The image beam is converted by a light valve from an illumination beam irradiating the light valve. The projection lens includes a first lens group, a second lens group, and a third lens group. The first lens group is disposed on a transmission path of the image beam, and has a first optical axis. The second lens group is disposed on both a transmission path of the illumination beam and the transmission path of the image beam, and between the light valve and the first lens group. The second lens group has a second optical axis. The second optical axis is inclined with respect to the first optical axis. The third lens group is disposed on the transmission path of the image beam, and between the first lens group and the second lens group. A projection apparatus is also provided.

摘要翻译： 提供了用于投影图像束的投影透镜。 图像光束通过光阀从照射光阀的照明光束转换。 投影透镜包括第一透镜组，第二透镜组和第三透镜组。 第一透镜组设置在图像束的传输路径上，并且具有第一光轴。 第二透镜组设置在照明光束的传输路径和图像束的传输路径之间，以及光阀和第一透镜组之间。 第二透镜组具有第二光轴。 第二光轴相对于第一光轴倾斜。 第三透镜组设置在图像束的传输路径上，并且位于第一透镜组和第二透镜组之间。 还提供投影设备。

公开(公告)号：US08237286B2

公开(公告)日：2012-08-07

申请号：US12760594

申请日：2010-04-15

申请人： Hanyi Ding ,  Ronald G. Filippi ,  Jong-Ru Guo ,  Ping-Chuan Wang

发明人： Hanyi Ding ,  Ronald G. Filippi ,  Jong-Ru Guo ,  Ping-Chuan Wang

IPC分类号： H01L23/522

CPC分类号： H01L23/528 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.

摘要翻译： 一种集成电路（IC）互连结构，其包括位于电介质中并且在一端耦合到高电流器件的第一通孔和位于电介质中的缓冲金属段，并在其相对端耦合到第一通孔。 缓冲金属段包括在其上形成ILD干酪糖化图案的多个电绝缘介电层（ILD）焊盘以引导电流。 IC互连结构还包括位于介质上的第二通孔，该电介质形成在缓冲金属段上并且在一端耦合到缓冲金属段，并且金属电源线形成在电介质中，并在其相对端耦合到第二通孔。 缓冲金属片段上的ILD焊盘的使用使得能够沿着金属电源线更均匀地分布电流。

公开(公告)号：US08232646B2

公开(公告)日：2012-07-31

申请号：US12691213

申请日：2010-01-21

申请人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  Chao-Kun Hu ,  Naftali E. Lustig ,  Andrew H. Simon ,  Ping-Chuan Wang

发明人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  Chao-Kun Hu ,  Naftali E. Lustig ,  Andrew H. Simon ,  Ping-Chuan Wang

IPC分类号： H01L23/48

CPC分类号： H01L23/5226 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76846 ,  H01L21/76847 ,  H01L23/522 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure for an integrated circuit (IC) device includes a metal line formed within a dielectric layer, the metal line having one or more vertical diffusion barriers therein; wherein the one or more vertical diffusion barriers correspond to a liner material of a via formed above the metal line, with the via extending completely through a thickness of the metal line such that a bottom most portion of the via comprises a portion of the metal line.

摘要翻译： 用于集成电路（IC）器件的互连结构包括形成在电介质层内的金属线，所述金属线在其中具有一个或多个垂直扩散阻挡层; 其中所述一个或多个垂直扩散屏障对应于在所述金属线上方形成的通孔的衬垫材料，所述通孔完全延伸穿过所述金属线的厚度，使得所述通孔的最底部包括所述金属线的一部分 。

公开(公告)号：US08232115B2

公开(公告)日：2012-07-31

申请号：US12566726

申请日：2009-09-25

申请人： Hanyi Ding ,  Kai D. Feng ,  Ping-Chuan Wang ,  Zhijian Yang

发明人： Hanyi Ding ,  Kai D. Feng ,  Ping-Chuan Wang ,  Zhijian Yang

IPC分类号： H01L21/66

CPC分类号： H01L22/34 ,  H01L21/76898

摘要： A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel. A method of determining a depth of a through-silicon-via (TSV) in a semiconductor chip includes etching a first TSV into the semiconductor chip; forming a first channel, the first channel comprising the first TSV, a first contact electrically connected to the first TSV, and a second contact; connecting a current source to the second contact; determining a resistance across the first channel; and determining a depth of the first TSV based on the resistance of the first channel.

摘要翻译： 半导体芯片中的贯穿硅通孔（TSV）的测试结构包括：第一触点，第一触点电连接到第一TSV; 以及第二触点，其中所述第一触点，所述第二触点和所述第一TSV形成第一通道，并且基于所述第一通道的电阻来确定所述第一TSV的深度。 确定半导体芯片中的硅通孔（TSV）的深度的方法包括将第一TSV蚀刻到半导体芯片中; 形成第一通道，所述第一通道包括所述第一TSV，电连接到所述第一TSV的第一触点和第二触点; 将电流源连接到第二触点; 确定跨越第一通道的电阻; 以及基于所述第一通道的电阻确定所述第一TSV的深度。