公开(公告)号：US20130055190A1

公开(公告)日：2013-02-28

申请号：US13523874

申请日：2012-06-14

Applicant: DAN-CHEN WU ,  SHOU-KUO HSU ,  CHUN-JEN CHEN

Inventor： DAN-CHEN WU ,  SHOU-KUO HSU ,  CHUN-JEN CHEN

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F2217/78

Abstract: A computing device reads a printed circuit board (PCB) layout file from a storage device. The PCB layout file includes arrangement information of signal lines, power lines, and power through-holes arranged on a PCB. Furthermore, the computing device sets a reference distance between a selected power through-hole and a neighboring signal line, and searches for one or more line segments of one or more signal lines where the a distance between each of the one or more line segment and the selected power through-hole is less than the reference distance.

Abstract translation: 计算设备从存储设备读取印刷电路板（PCB）布局文件。 PCB布局文件包括布置在PCB上的信号线，电源线和电源通孔的布置信息。 此外，计算装置设置所选功率通孔和相邻信号线之间的参考距离，并且搜索一个或多个信号线的一个或多个线段，其中，所述一个或多个线段中的每一个之间的距离和 所选功率通孔小于参考距离。

公开(公告)号：US08383955B2

公开(公告)日：2013-02-26

申请号：US13097104

申请日：2011-04-29

Applicant: Tsung-Sheng Huang ,  Chun-Jen Chen ,  Duen-Yi Ho ,  Wei-Chieh Chou

Inventor： Tsung-Sheng Huang ,  Chun-Jen Chen ,  Duen-Yi Ho ,  Wei-Chieh Chou

IPC: H05K1/11

CPC classification number: H05K1/025 ,  H05K1/0265 ,  H05K3/429 ,  H05K2201/0979

Abstract: A printed circuit board (PCB) includes first to fourth layers. A power supply is arranged on the first layer. An electronic component is arranged on the fourth layer. A first via and a second via extend through the PCB and are electrically connected to the electronic component. The PCB further includes third to seventh vias. A length of a transmission path of the current flows from the power supply to electronic component through the third via and the seventh via is almost the same as a length of a transmission path of the current flows from the power supply to the electronic component through the fourth to sixth vias.

Abstract translation: 印刷电路板（PCB）包括第一至第四层。 电源设置在第一层上。 电子部件布置在第四层上。 第一通孔和第二通孔延伸穿过PCB并且电连接到电子部件。 PCB还包括第三至第七个通孔。 通过第三通孔和第七通孔从电源流向电子部件的电流的传输路径的长度与电流从电源流向电子部件的传输路径的长度几乎相同 第四至第六个通道。

公开(公告)号：US20120268086A1

公开(公告)日：2012-10-25

申请号：US13340707

申请日：2011-12-30

Applicant: WEI-CHIEH CHOU ,  DUEN-YI HO ,  CHUN-JEN CHEN ,  TSUNG-SHENG HUANG

Inventor： WEI-CHIEH CHOU ,  DUEN-YI HO ,  CHUN-JEN CHEN ,  TSUNG-SHENG HUANG

IPC: G05F1/12 ,  H03F3/45

CPC classification number: H02M3/33523 ,  H02M2001/0003

Abstract: A power supply device includes a power supply unit and a feedback control unit. The power supply unit is configured for generating an electric potential to be provided to a load. The feedback control unit detects the electric potential and adjusts relevant parameters of the electrical potential to achieve predetermined values. The feedback control unit includes a first feedback circuit and a second feedback circuit electrically connected in series.

Abstract translation: 电源装置包括电源单元和反馈控制单元。 电源单元被配置为产生要提供给负载的电位。 反馈控制单元检测电位并调整电位的相关参数以实现预定值。 反馈控制单元包括串联电连接的第一反馈电路和第二反馈电路。

公开(公告)号：US08101586B2

公开(公告)日：2012-01-24

申请号：US12769983

申请日：2010-04-29

Applicant: Kenneth L. Rock ,  Chun-Jen Chen

Inventor： Kenneth L. Rock ,  Chun-Jen Chen

IPC: A61K48/00

CPC classification number: A61K31/7088 ,  G01N33/5008 ,  G01N33/6869 ,  G01N2333/4703

Abstract: Described are methods and compositions that inhibit IL-1 signalling for the treatment of acute inflammatory response to cell necrosis, and the attendant collateral tissue damage.

Abstract translation: 描述了抑制IL-1信号传导治疗对细胞坏死的急性炎症反应以及伴随的侧支组织损伤的方法和组合物。

公开(公告)号：US20110273235A1

公开(公告)日：2011-11-10

申请号：US12775486

申请日：2010-05-07

Applicant: Chun-Jen Chen ,  Chih-Chang Lee

Inventor： Chun-Jen Chen ,  Chih-Chang Lee

IPC: H03F3/68

CPC classification number: H03F3/24 ,  H03F1/0266 ,  H03F3/195 ,  H03F2200/336 ,  H03F2200/451 ,  H03F2200/555

Abstract: The present disclosure illustrates a feedforward controlled envelope modulator and a feedforward control circuit thereof. The feedforward controlled envelope modulator comprises a linear amplifier circuit, a switching amplifier, and a feedforward control circuit. The linear amplifier circuit amplifies an input voltage signal, so as to output an output voltage signal to a load node. The switching amplifier receives a comparison signal, and outputs a switching current to the load node according to the comparison signal. The feedforward control circuit comprises a duplicate linear amplifier circuit and a hysteresis comparator. The duplicate linear amplifier circuit amplifies the input voltage signal, so as to output a reference voltage signal, wherein an amplifying gain of the duplicate linear amplifier circuit is identical to an amplifying gain of the linear amplifier circuit. The hysteresis comparator compares the output voltage signal and the reference voltage signal, so as to output the comparison signal.

Abstract translation: 本公开示出了前馈控制包络调制器及其前馈控制电路。 前馈控制包络调制器包括线性放大器电路，开关放大器和前馈控制电路。 线性放大器电路放大输入电压信号，以将输出电压信号输出到负载节点。 开关放大器接收比较信号，并根据比较信号将负载节点输出开关电流。 前馈控制电路包括一个重复的线性放大器电路和一个滞后比较器。 重复的线性放大器电路放大输入电压信号，以便输出参考电压信号，其中重复线性放大器电路的放大增益与线性放大器电路的放大增益相同。 迟滞比较器比较输出电压信号和参考电压信号，以输出比较信号。

公开(公告)号：US20110238233A1

公开(公告)日：2011-09-29

申请号：US12774685

申请日：2010-05-05

Applicant: TSUNG-SHENG HUANG ,  CHUN-JEN CHEN ,  DUEN-YI HO ,  WEI-CHIEH CHOU

Inventor： TSUNG-SHENG HUANG ,  CHUN-JEN CHEN ,  DUEN-YI HO ,  WEI-CHIEH CHOU

IPC: G06F19/00

CPC classification number: G06F17/5063

Abstract: A system for optimizing a current overload protection circuit includes an input device, a data storage device, a central processing device, and a display. The central processing device includes a storage module, a control module, and a calculation module. The storage module stores a VI application therein. The control module receives instructions from the input device and selects virtual electronic components of the current overload protection circuit from the data storage device and connection of the selected electronic components. The current overload protection circuit is completed and run in the VI application; electronic components significantly affecting the maximum protection current are labeled. The calculation module calculates normal distribution samples of the current overload protection circuit based on the labeled electronic components. The display shows whether the current overload protection circuit meets a process capability standard.

Abstract translation: 用于优化电流过载保护电路的系统包括输入装置，数据存储装置，中央处理装置和显示器。 中央处理装置包括存储模块，控制模块和计算模块。 存储模块在其中存储VI应用。 控制模块从输入设备接收指令，并从数据存储设备中选择电流过载保护电路的虚拟电子部件，并选择电子部件的连接。 电流过载保护电路在VI应用中完成并运行; 显着影响最大保护电流的电子元件被标记。 计算模块基于标记的电子元件计算电流过载保护电路的正态分布样本。 显示屏显示电流过载保护电路是否符合过程能力标准。

公开(公告)号：US20110161893A1

公开(公告)日：2011-06-30

申请号：US12976646

申请日：2010-12-22

Applicant: CHIN-HSIANG LIN ,  Heng-Jen Lee ,  I-Hsiung Huang ,  Chih-Chiang Tu ,  Chun-Jen Chen ,  Rick Lai

Inventor： CHIN-HSIANG LIN ,  Heng-Jen Lee ,  I-Hsiung Huang ,  Chih-Chiang Tu ,  Chun-Jen Chen ,  Rick Lai

IPC: G06F17/50

CPC classification number: G03F1/72 ,  G03F1/86

Abstract: The present disclosure provides for many different embodiments. An exemplary method can include providing a mask fabricated according to a design pattern; extracting a mask pattern from the mask; converting the mask pattern into a rendered mask pattern, wherein the simulated design pattern includes the design pattern and any defects in the mask; simulating a lithography process using the rendered mask pattern to create a virtual wafer pattern; and determining whether any defects in the mask are critical based on the virtual wafer pattern. The critical defects in the mask can be repaired.

Abstract translation: 本公开提供了许多不同的实施例。 示例性方法可以包括提供根据设计图案制造的掩模; 从掩模中提取掩模图案; 将掩模图案转换成渲染的掩模图案，其中模拟设计图案包括设计图案和掩模中的任何缺陷; 使用所渲染的掩模图案来模拟光刻工艺以产生虚拟晶片图案; 以及基于所述虚拟晶片图案确定所述掩模中的任何缺陷是否是关键的。 面罩中的关键缺陷可以修复。

公开(公告)号：US07609424B2

公开(公告)日：2009-10-27

申请号：US10034860

申请日：2001-12-27

Applicant: Chun-Jen Chen ,  Shih-Huang Chen

Inventor： Chun-Jen Chen ,  Shih-Huang Chen

IPC: H04N1/46

CPC classification number: H04N1/40012

Abstract: A circuit of a scanner to perform a color space conversion on an RGB signal. The circuit has several sampling-amplified-offset devices to sample, amplify and compensate potential of an R charge signal, a G charge signal and a B charge signal to obtain an R analog signal, a G analog signal and a B analog signal. The circuit further has a gain adder to multiply the corresponding weighted gain with the R analog signal, the G analog signal and the B analog signal. The multiplication results are then summed up to obtain an addition analog signal. A multiplexer is also included to select between the R analog signal, the G analog signal, the B analog signal and the addition analog signal for output.

Abstract translation: 扫描仪的电路，用于对RGB信号进行色彩空间转换。 该电路具有多个采样放大偏移器件，用于对R充电信号，G充电信号和B充电信号的电位进行采样，放大和补偿，以获得R模拟信号，G模拟信号和B模拟信号。 该电路还具有增益加法器，以将相应的加权增益与R模拟信号，G模拟信号和B模拟信号相乘。 然后将相乘结果相加以获得加法模拟信号。 还包括多路复用器，用于在R模拟信号，G模拟信号，B模拟信号和加法模拟信号之间选择输出。

公开(公告)号：US07446913B2

公开(公告)日：2008-11-04

申请号：US10064704

申请日：2002-08-08

Applicant: Chun-Jen Chen ,  Shang-Yu Yang ,  Chun-I Hsiao ,  Tse-Hui Pang

Inventor： Chun-Jen Chen ,  Shang-Yu Yang ,  Chun-I Hsiao ,  Tse-Hui Pang

IPC: H04N1/46

CPC classification number: H04N1/0286 ,  H04N1/02815 ,  H04N1/0287 ,  H04N1/02895 ,  H04N2201/02493 ,  H04N2201/02495

Abstract: An image compensation method is provided. At least one light source and a plurality of reflecting elements each capable of reflecting light from the light source are provided. Each reflecting element reflects a beam of light from the light source to produce a beam of reflected light having a unique color content. The reflecting elements are shifted to a location where one of the reflecting elements is capable of reflecting light from the light source.

Abstract translation: 提供了一种图像补偿方法。 提供了能够反射来自光源的光的至少一个光源和多个反射元件。 每个反射元件反射来自光源的光束以产生具有独特颜色含量的反射光束。 反射元件移动到其中一个反射元件能够反射来自光源的光的位置。

公开(公告)号：US20080073753A1

公开(公告)日：2008-03-27

申请号：US11525575

申请日：2006-09-22

Applicant: Hao-Yi Tsai ,  Chia-Lun Tsai ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Shih-Hsun Hsu ,  Wei-Ti Hsu ,  Lin-Ko Feng ,  Chun-Jen Chen

Inventor： Hao-Yi Tsai ,  Chia-Lun Tsai ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Shih-Hsun Hsu ,  Wei-Ti Hsu ,  Lin-Ko Feng ,  Chun-Jen Chen

IPC: H01L23/544

CPC classification number: H01L21/78 ,  H01L21/782 ,  H01L21/784 ,  H01L21/786 ,  H01L22/10 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor wafer structure includes a plurality of dies, a first scribe line extending along a first direction, a second scribe line extending along a second direction and intersecting the first scribe line, wherein the first and the second scribe lines have an intersection region. A test line is formed in the scribe line, wherein the test line crosses the intersection region. Test pads are formed in the test line and only outside a free region defined substantially in the intersection region.

Abstract translation: 半导体晶片结构包括多个模具，沿着第一方向延伸的第一划线，沿着第二方向延伸并且与第一划线交叉的第二划线，其中第一划线和第二划线具有交叉区域。 在划线中形成测试线，其中测试线穿过交叉区域。 测试垫形成在测试线中，并且仅在基本上在交叉区域中限定的自由区域的外部。