公开(公告)号：US07550795B2

公开(公告)日：2009-06-23

申请号：US11477953

申请日：2006-06-30

Applicant: Chung-Long Cheng ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Tzung-Chi Lee ,  Harry Chuang

Inventor： Chung-Long Cheng ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Tzung-Chi Lee ,  Harry Chuang

IPC: H01L29/76

CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/4238 ,  H01L29/78636

Abstract: Silicon on insulator (SOI) devices and methods for fabricating the same are provided. An exemplary embodiment of a SOI device comprises a substrate. A first insulating layer is formed over the substrate. A plurality of semiconductor islands is formed over the first insulating layer, wherein the semiconductor islands are isolated from each other. A second insulating layer is formed over the first insulating layer, protruding over the semiconductor islands and surrounding thereof. At least one recess is formed in a portion of the second insulating layer adjacent to a pair of the semiconductor islands. A first dielectric layer is formed on a portion of each of the semiconductor islands. A conductive layer is formed over the first dielectric layer and over the second insulating layer exposed by the recess. A pair of source/drain regions is oppositely formed in portions of each of the semiconductor islands not covered by the first dielectric layer and the conductive layer.

Abstract translation: 提供绝缘体上硅（SOI）器件及其制造方法。 SOI器件的示例性实施例包括衬底。 在衬底上形成第一绝缘层。 在第一绝缘层上形成多个半导体岛，其中半导体岛彼此隔离。 在第一绝缘层上形成第二绝缘层，突出在半岛上并围绕它们。 在与一对半导体岛相邻的第二绝缘层的一部分中形成至少一个凹部。 第一电介质层形成在每个半导体岛的一部分上。 导电层形成在第一电介质层之上，并在由凹部露出的第二绝缘层之上。 一对源极/漏极区域相对地形成在未被第一介电层和导电层覆盖的半导体岛的每一个的部分中。

公开(公告)号：US20080315320A1

公开(公告)日：2008-12-25

申请号：US11766425

申请日：2007-06-21

Applicant: Chung Long Cheng ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang ,  Mong Song Liang

Inventor： Chung Long Cheng ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang ,  Mong Song Liang

IPC: H01L29/76 ,  H01L27/12 ,  H01L27/01 ,  H01L31/0392

CPC classification number: H01L29/66477 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/7848

Abstract: A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.

Abstract translation: 具有具有高k栅极电介质的核心器件和具有二氧化硅或其它非高k栅极电介质的I / O器件的半导体器件及其制造方法。 核心阱和I / O阱在半导体衬底中产生并被隔离结构隔开。 I / O器件形成在I / O阱上，并具有二氧化硅或低k栅极电介质。 可以在与芯井相邻的隔离结构上形成电阻器。 在核心阱上形成诸如晶体管的核心阱器件，并且具有高k栅极电介质。 在一些实施例中，产生p型I / O阱和n型I / O阱。 在优选实施例中，在形成核心器件之前形成I / O器件或器件，并用牺牲层进行保护，直到制造核心器件。

公开(公告)号：US20080296691A1

公开(公告)日：2008-12-04

申请号：US11807654

申请日：2007-05-30

Applicant: Harry Chuang ,  Kong-Beng Thei ,  Jen-Bin Hsu ,  Chung Long Cheng ,  Mong Song Liang

Inventor： Harry Chuang ,  Kong-Beng Thei ,  Jen-Bin Hsu ,  Chung Long Cheng ,  Mong Song Liang

IPC: H01L29/76

CPC classification number: H01L27/0207 ,  H01L27/11 ,  H01L27/1104

Abstract: A semiconductor structure includes an array of unit metal-oxide-semiconductor (MOS) devices arranged in a plurality of rows and a plurality of columns is provided. Each of the unit MOS devices includes an active region laid out in a row direction and a gate electrode laid out in a column direction. The semiconductor structure further includes a first unit MOS device in the array and a second unit MOS device in the array, wherein active regions of the first and the second unit MOS devices have different conductivity types.

Abstract translation: 半导体结构包括以多行排列的单位金属氧化物半导体（MOS）器件的阵列，并且提供多个列。 每个单位MOS器件包括布置在行方向上的有源区和沿列方向布置的栅电极。 半导体结构还包括阵列中的第一单元MOS器件和阵列中的第二单元MOS器件，其中第一和第二单位MOS器件的有源区具有不同的导电类型。

公开(公告)号：US20080263492A1

公开(公告)日：2008-10-23

申请号：US11833119

申请日：2007-08-02

Applicant: Harry Chuang ,  Kong-Beng Thei ,  Mong Song Liang ,  Sheng-Chen Chung ,  Chih-Tsung Yao ,  Jung-Hui Kao ,  Chung Long Cheng ,  Gary Shen ,  Gwan Sin Chang

Inventor： Harry Chuang ,  Kong-Beng Thei ,  Mong Song Liang ,  Sheng-Chen Chung ,  Chih-Tsung Yao ,  Jung-Hui Kao ,  Chung Long Cheng ,  Gary Shen ,  Gwan Sin Chang

IPC: G06F17/50

CPC classification number: H01L29/785 ,  H01L21/76807 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

Abstract: A method for defining a layout of 3-D devices, such as a finFET, is provided. The method includes determining an area required by a desired 3-D device and designing a circuit using planar devices having an equivalent area. The planar device corresponding to the desired 3-D device is used to layout a circuit design, thereby allowing circuit and layout designers to work at a higher level without the need to specify each individual fin or 3-D structure. Thereafter, the planar design may be converted to a 3-D design by replacing planar active areas with 3-D devices occupying an equivalent area.

Abstract translation: 提供了一种用于定义诸如finFET的3-D器件的布局的方法。 该方法包括确定期望的3-D设备所需的区域和使用具有等效面积的平面设备来设计电路。 对应于期望的3-D器件的平面器件用于布局电路设计，从而允许电路和布局设计者在更高级别工作，而不需要指定每个单独的鳍或3-D结构。 此后，平面设计可以通过用占据等同面积的3-D器件代替平面有源区域而被转换成3维设计。

公开(公告)号：US20080258228A1

公开(公告)日：2008-10-23

申请号：US11833128

申请日：2007-08-02

Applicant: Harry Chuang ,  Kong-Beng Thei ,  Mong Song Liang ,  Jung-Hui Kao ,  Sheng-Chen Chung ,  Chung Long Cheng ,  Shun-Jang Liao

Inventor： Harry Chuang ,  Kong-Beng Thei ,  Mong Song Liang ,  Jung-Hui Kao ,  Sheng-Chen Chung ,  Chung Long Cheng ,  Shun-Jang Liao

IPC: H01L29/78 ,  H01L21/8238

CPC classification number: H01L29/785 ,  H01L21/76807 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

Abstract: A semiconductor structure and methods of forming the same are provided. The semiconductor structure includes a semiconductor substrate; a first inter-layer dielectric (ILD) over the semiconductor substrate; a contact extending from a top surface of the first ILD into the first ILD; a second ILD over the first ILD; a bottom inter-metal dielectric (IMD) over the second ILD; and a dual damascene structure comprising a metal line in the IMD and a via in the second ILD, wherein the via is connected to the contact.

Abstract translation: 提供半导体结构及其形成方法。 半导体结构包括半导体衬底; 半导体衬底上的第一层间电介质（ILD）; 从第一ILD的顶表面延伸到第一ILD中的接触; 第一个ILD的第二个ILD; 在第二ILD上的底部金属间电介质（IMD）; 以及包括IMD中的金属线和第二ILD中的通孔的双镶嵌结构，其中所述通孔连接到所述触点。

公开(公告)号：US20080020533A1

公开(公告)日：2008-01-24

申请号：US11490012

申请日：2006-07-20

Applicant: Kong-Beng Thei ,  Chung Long Cheng ,  Harry Chuang

Inventor： Kong-Beng Thei ,  Chung Long Cheng ,  Harry Chuang

IPC: H01L21/336

CPC classification number: H01L21/26586 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843

Abstract: A semiconductor device with improved source/drain junctions and methods for fabricating the device are disclosed. A preferred embodiment comprises a MOS transistor with a gate structure overlying a substrate, lightly doped source/drain regions formed in the substrate aligned to the gate structure, sidewall spacers formed on the sidewalls of the gate structure and overlying the lightly doped source/drain regions, deeper source/drain diffusions formed into the substrate aligned to the sidewall spacers and additional pocket implants of source/drain dopants formed at the boundary of the deeper source/drain diffusions and the substrate. In a preferred method, the additional pocket implants are formed using an angled ion implant with the angle being between 4 and 45 degrees from vertical. Additional embodiments include recesses formed in the source/drain regions and methods for forming the recesses.

Abstract translation: 公开了一种具有改善的源极/漏极结的半导体器件和用于制造器件的方法。 优选实施例包括具有覆盖在衬底上的栅极结构的MOS晶体管，形成在衬底中的与栅极结构对准的轻掺杂源极/漏极区域，形成在栅极结构的侧壁上并叠置在轻掺杂源极/漏极区域 形成在衬底中的更深的源极/漏极扩散与侧壁间隔物对准，并且在较深的源极/漏极扩散和衬底的边界处形成的源极/漏极掺杂剂的另外的凹穴注入。 在优选的方法中，使用角度离子植入物形成额外的袋状植入物，该角度离垂直方向在4度和45度之间。 另外的实施例包括在源极/漏极区域中形成的凹部和用于形成凹部的方法。

公开(公告)号：US07157351B2

公开(公告)日：2007-01-02

申请号：US10850747

申请日：2004-05-20

Applicant: Chung-Long Cheng ,  Kong-Beng Thei ,  Jung-Hui Kao

Inventor： Chung-Long Cheng ,  Kong-Beng Thei ,  Jung-Hui Kao

IPC: H01L21/76

CPC classification number: H01L21/02057 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02304 ,  H01L21/02307 ,  H01L21/31662 ,  H01L21/76224

Abstract: A method for cleaning and forming an oxide film on a surface, particularly a silicon surface. The surface is initially cleaned and then exposed to ozone vapor, which forms the oxide film on the surface. The method is particularly useful for forming a pre-liner oxide film on trench surfaces in the fabrication of STI (shallow trench isolation) structures.

Abstract translation: 一种在表面特别是硅表面上清洗和形成氧化膜的方法。 表面最初被清洁，然后暴露于臭氧蒸汽，这在表面上形成氧化膜。 该方法在STI（浅沟槽隔离）结构的制造中在沟槽表面上形成预衬垫氧化膜特别有用。

公开(公告)号：US20060220181A1

公开(公告)日：2006-10-05

申请号：US11097743

申请日：2005-04-01

Applicant: Chung-Long Cheng ,  Kong-Beng Thei ,  Sheng-Yuan Lin

Inventor： Chung-Long Cheng ,  Kong-Beng Thei ,  Sheng-Yuan Lin

IPC: H01L29/93

CPC classification number: H01L29/93 ,  H01L27/0808 ,  H01L29/417

Abstract: A dummy region varactor for improving a CMP process and improving electrical isolation from active areas and a method for forming the same, the varactor including a semiconductor substrate having a dummy region said dummy region including a first well region having a first polarity; shallow trench isolation (STI) structures disposed in the dummy region defining adjacent mesa regions comprising first, second, and third mesa regions; a second well region having a second polarity underlying the first mesa region having the second polarity to form a PN junction interface; wherein said second and third mesa regions having the first polarity are formed adjacent either side of said first mesa region.

公开(公告)号：US07026195B2

公开(公告)日：2006-04-11

申请号：US10851376

申请日：2004-05-21

Applicant: Chung-Long Cheng ,  Kong-Beng Thei

Inventor： Chung-Long Cheng ,  Kong-Beng Thei

IPC: H01L21/00 ,  H01L21/302

CPC classification number: H01L29/785 ,  H01L21/32139 ,  H01L29/42384 ,  H01L29/66795

Abstract: A method for forming a FIN-FET device employs a blanket planarizing layer formed upon a blanket topographic gate electrode material layer. The blanket planarizing layer is patterned and employed as a mask layer for patterning the blanket topographic gate electrode material layer to form a gate electrode. Since the blanket planarizing layer is formed as a planarizing layer, a photoresist layer formed thereupon is formed with enhanced resolution. As a result, the gate electrode is also formed with enhanced resolution. A resulting FIN-FET structure has the patterned planarizing layer formed in an inverted “U” shape upon the gate electrode.

Abstract translation: 用于形成FIN-FET器件的方法使用形成在覆盖的地形栅电极材料层上的覆盖平坦化层。 图案化覆盖层平坦化层并用作掩模层，用于图案化覆盖层形成的栅电极材料层以形成栅电极。 由于覆盖平坦化层形成为平坦化层，所以在其上形成的光致抗蚀剂层以更高的分辨率形成。 结果，栅电极也形成了增强的分辨率。 所得到的FIN-FET结构具有在栅电极上以倒U形形成的图案化平坦化层。

公开(公告)号：US08803202B2

公开(公告)日：2014-08-12

申请号：US13558109

申请日：2012-07-25

Applicant: Harry-Hak-Lay Chuang ,  Kong-Beng Thei ,  Jen-Bin Hsu ,  Chung Long Cheng ,  Mong-Song Liang

Inventor： Harry-Hak-Lay Chuang ,  Kong-Beng Thei ,  Jen-Bin Hsu ,  Chung Long Cheng ,  Mong-Song Liang

IPC: H01L27/118

CPC classification number: H01L27/0207 ,  H01L27/11 ,  H01L27/1104

Abstract: A semiconductor structure includes an array of unit metal-oxide-semiconductor (MOS) devices arranged in a plurality of rows and a plurality of columns is provided. Each of the unit MOS devices includes an active region laid out in a row direction and a gate electrode laid out in a column direction. The semiconductor structure further includes a first unit MOS device in the array and a second unit MOS device in the array, wherein active regions of the first and the second unit MOS devices have different conductivity types.

Abstract translation: 半导体结构包括以多行排列的单位金属氧化物半导体（MOS）器件的阵列，并且提供多个列。 每个单位MOS器件包括布置在行方向上的有源区和沿列方向布置的栅电极。 半导体结构还包括阵列中的第一单元MOS器件和阵列中的第二单元MOS器件，其中第一和第二单位MOS器件的有源区具有不同的导电类型。