公开(公告)号：US20220320326A1

公开(公告)日：2022-10-06

申请号：US17613628

申请日：2020-07-21

Applicant: ENKRIS SEMICONDUCTOR, INC.

Inventor： Kai Cheng

IPC: H01L29/778 ,  H01L29/15 ,  H01L29/20 ,  H01L29/205

Abstract: The present application provides a semiconductor structure. The semiconductor structure includes a channel layer and a barrier layer provided on the channel layer. The barrier layer includes multiple barrier layers arranged in a stack, the multiple barrier sub-layers include at least three barrier sub-layers, and Al component proportions of the multiple barrier sub-layers vary along a growth direction of the barrier layer for at least one up-and-down fluctuation.

公开(公告)号：US20210399122A1

公开(公告)日：2021-12-23

申请号：US17465690

申请日：2021-09-02

Applicant: Yu Zhu ,  ENKRIS SEMICONDUCTOR, INC.

Inventor： Kai CHENG ,  Yu ZHU

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/66

Abstract: The present application provides a semiconductor structure and a method for manufacturing the same, which solves a problem that an existing semiconductor structure is difficult to deplete a carrier concentration of a channel under a gate to realize an enhancement mode device. The semiconductor structure includes: a channel layer and a barrier layer superimposed in sequence, wherein a gate region is defined on a surface of the barrier layer; a plurality of trenches formed in the gate region, wherein the plurality of trenches extend into the channel layer; and a P-type semiconductor material filling the plurality of trenches.

公开(公告)号：US10998435B2

公开(公告)日：2021-05-04

申请号：US16705641

申请日：2019-12-06

Applicant: ENKRIS SEMICONDUCTOR, INC.

Inventor： Kai Cheng

IPC: H01L29/778 ,  H01L21/02 ,  H01L21/306 ,  H01L29/04 ,  H01L29/08 ,  H01L29/20 ,  H01L29/205 ,  H01L29/267 ,  H01L29/36 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: An enhancement-mode device includes: a substrate; a channel layer and a barrier layer successively formed on the substrate; an n-type semiconductor layer formed on the barrier layer, a gate region being defined on a surface of the n-type semiconductor layer; a groove that is formed in the gate region and at least partially runs through the n-type semiconductor layer; and a p-type conductor material that is formed on the surface of the n-type semiconductor layer and at least fills the inside of the groove.

公开(公告)号：US20210057560A1

公开(公告)日：2021-02-25

申请号：US17086709

申请日：2020-11-02

Applicant: ENKRIS SEMICONDUCTOR, INC.

Inventor： Kai CHENG

IPC: H01L29/778 ,  H01L29/15 ,  H01L29/20 ,  H01L29/205 ,  H01L29/207 ,  H01L21/306 ,  H01L29/66

Abstract: Embodiments of the present application disclose a semiconductor structure and a manufacturing method for the semiconductor structure, which solve problems of complicated manufacturing process and poor stability and reliability of existing semiconductor structures. The semiconductor structure includes: a substrate; a channel layer, a barrier layer and a semiconductor layer sequentially superimposed on the substrate, wherein the semiconductor layer is made of a GaN-based material and an upper surface of the semiconductor layer is Ga-face; and a p-type GaN-based semiconductor layer, with N-face as an upper surface, formed in a gate region of the semiconductor layer.

公开(公告)号：US10916445B2

公开(公告)日：2021-02-09

申请号：US16441586

申请日：2019-06-14

Applicant: ENKRIS SEMICONDUCTOR, INC.

Inventor： Kai Cheng

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/324 ,  H01L29/207 ,  H01L29/778

Abstract: A method for preparing a p-type semiconductor layer, an enhanced device and a method for manufacturing the same disclosed relate to the technical field of microelectronics. The method for preparing a p-type semiconductor layer includes: preparing a p-type semiconductor layer; preparing a protective layer on the p-type semiconductor layer, in which the protective layer is made of AlN or AlGaN; and annealing the p-type semiconductor layer under protection of the protective layer. In this way, the protective layer can protect the p-type semiconductor layer from volatilization and to form high-quality surface morphology in the subsequent high-temperature annealing treatment of the p-type semiconductor layer.

公开(公告)号：US20190214467A1

公开(公告)日：2019-07-11

申请号：US16099177

申请日：2017-04-24

Applicant: ENKRIS SEMICONDUCTOR, INC

Inventor： Kai CHENG ,  Peng XIANG

IPC: H01L29/15 ,  H01L29/20 ,  H01L21/02 ,  H01L29/205 ,  H01L23/00

Abstract: The invention provides a semiconductor structure and a method of preparing a semiconductor structure, which solves the problems of easy cracking, large warpage and large dislocation density which exist in epitaxial growth of a semiconductor compound epitaxial structure on a substrate in the prior art. The semiconductor structure includes: a substrate; at least one periodic structure disposed over the substrate; wherein each of the periodic structures includes at least one period, each period including a first periodic layer and a second periodic layer which are sequentially stacked in an epitaxial direction; wherein the thickness of the nth periodic structure is smaller than the thickness of the (n+1)th periodic structure, wherein n is an integer greater than or equal to 1.

公开(公告)号：US20190081010A1

公开(公告)日：2019-03-14

申请号：US16184998

申请日：2018-11-08

Applicant: ENKRIS SEMICONDUCTOR, INC.

Inventor： Peng XIANG ,  Kai CHENG

IPC: H01L23/00 ,  H01L29/20 ,  H01L33/12 ,  H01L33/32 ,  H01L21/02

Abstract: The present invention discloses a semiconductor structure and a method for manufacturing the semiconductor structure. The semiconductor structure includes: a substrate; and at least one composition adjusting layer disposed above the substrate; wherein each of the at least one composition adjusting layer is made of a semiconductor compound, the semiconductor compound at least comprises a first element and a second element, and an atomic number of the first element is less than an atomic number of the second element, wherein in each of the at least one composition adjusting layer, along an epitaxial direction of the substrate, an atomic percentage of the first element in a compound composition is gradually decreased at first and then gradually increased, a thickness of a gradual decrease section is greater than a thickness of a gradual increase section.

公开(公告)号：US20190051697A1

公开(公告)日：2019-02-14

申请号：US15763610

申请日：2017-01-12

Applicant: Enkris Semiconductor, Inc.

Inventor： Liyang Zhang

IPC: H01L27/15 ,  H01L33/62 ,  H01L33/46 ,  H01L33/38 ,  H01L33/44 ,  H01L33/50 ,  H01L33/00

CPC classification number: H01L27/156 ,  H01L33/007 ,  H01L33/0079 ,  H01L33/06 ,  H01L33/32 ,  H01L33/382 ,  H01L33/44 ,  H01L33/46 ,  H01L33/505 ,  H01L33/62 ,  H01L2933/0016 ,  H01L2933/0025 ,  H01L2933/0041 ,  H01L2933/0066

Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes: a substrate, a bonding metal layer, a reflective layer, a first conductive layer, an active layer, a second conductive layer, first electrode(s) and second electrode(s). The first electrode(s) extends, from one side of the bonding metal layer away from the substrate, to the first conductive layer, to be connected with the bonding metal layer and the first conductive layer. The second electrode(s) penetrates through the substrate and the bonding metal layer to be in contact with the reflective layer. The semiconductor device, forming a structure sharing the first conductive layer, has more uniform illumination and a higher light extraction rate, and eliminates interferences between pixel units, achieves better uniformity of emitted light wavelength and makes distribution of electric current flowing through different pixel units more even.

公开(公告)号：US09812540B2

公开(公告)日：2017-11-07

申请号：US14395338

申请日：2013-03-29

Applicant: Enkris Semiconductor, Inc.

Inventor： Kai Cheng

IPC: H01L29/778 ,  H01L29/423 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/40 ,  H01L29/20

CPC classification number: H01L29/4238 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/49 ,  H01L29/4925 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/7783

Abstract: An enhanced switch device and a manufacturing method therefor. The method comprises: providing a substrate, and forming a nitride transistor structure on the substrate; fabricating and forming a dielectric layer on the nitride transistor structure, on which a gate region is defined; forming a groove structure on the gate region; depositing a p-type semiconductor material in the groove; removing the p-type semiconductor material outside the gate region on the dielectric layer; etching the dielectric layer in another position than the gate region on the dielectric layer to form two ohmic contact regions; and forming a source electrode and a drain electrode on the two ohmic contact regions, respectively.

公开(公告)号：US20160315220A1

公开(公告)日：2016-10-27

申请号：US15201533

申请日：2016-07-04

Applicant: ENKRIS SEMICONDUCTOR, INC.

Inventor： Kai CHENG

IPC: H01L33/12 ,  H01L33/26 ,  H01L33/18 ,  H01L33/00

CPC classification number: H01L33/12 ,  H01L21/187 ,  H01L21/2007 ,  H01L33/0066 ,  H01L33/0075 ,  H01L33/18 ,  H01L33/26

Abstract: A semiconductor substrate, a semiconductor device and a manufacturing method of the semiconductor substrate are provided. The semiconductor substrate comprises a first semiconductor layer and a second semiconductor layer located on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer, as well as semiconductor layers obtained by symmetrically rotating the first semiconductor layer and the second semiconductor layer according to their respective lattice structures, have different cleavage planes in a vertical direction. By providing the semiconductor substrates having composite structures, even if thicknesses of the substrates are not changed, the damages to the semiconductor substrates due to stresses by the semiconductor epitaxial layers can be reduced, thereby decreasing the likelihood of breakage of the semiconductor substrates. Furthermore, the processing difficulty is reduced and the reliability of the semiconductor devices is improved.

Abstract translation: 提供半导体衬底，半导体器件和半导体衬底的制造方法。 半导体衬底包括位于第一半导体层上的第一半导体层和第二半导体层。 第一半导体层和第二半导体层以及根据其各自的晶格结构对称地旋转第一半导体层和第二半导体层而获得的半导体层在垂直方向上具有不同的解理面。 通过提供具有复合结构的半导体衬底，即使衬底的厚度没有改变，也可以减少由于半导体外延层的应力对半导体衬底的损伤，从而降低了半导体衬底的破裂的可能性。 此外，降低了处理难度，提高了半导体器件的可靠性。