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    Magnetoresistive structure having two dielectric layers, and method of manufacturing same
    31.
    发明授权
    Magnetoresistive structure having two dielectric layers, and method of manufacturing same 有权

    公开(公告)号：US10608172B2

    公开(公告)日：2020-03-31

    申请号：US16255912

    申请日：2019-01-24

    Applicant: Everspin Technologies, Inc.

    Inventor： Sanjeev Aggarwal ,  Kerry Nagel ,  Jason Janesky

    IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  G11C11/16 ,  H01L43/10

    Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. For example, an exemplary method of manufacturing a magnetoresistive device includes etching through a second electrode, second dielectric layer and free magnetic layer to provide a sidewall of (i) an unpinned synthetic antiferromagnetic structure, (ii) a second dielectric layer and (iii) a free magnetic layer; thereafter, forming an encapsulation material on the sidewall of the unpinned synthetic antiferromagnetic structure, second dielectric layer and free magnetic layer, and after forming the encapsulation material, etching through a first dielectric layer.

    SENSING APPARATUS FOR SENSING CURRENT THROUGH A CONDUCTOR AND METHODS THEREFOR
    32.
    发明申请
    SENSING APPARATUS FOR SENSING CURRENT THROUGH A CONDUCTOR AND METHODS THEREFOR 审中-公开

    公开(公告)号：US20200081037A1

    公开(公告)日：2020-03-12

    申请号：US16681907

    申请日：2019-11-13

    Applicant: Everspin Technologies, Inc.

    Inventor： Angelo Ugge ,  Markus Schwickert ,  David Hayner

    IPC: G01R15/20

    Abstract: A sensing apparatus for characterizing current flow through a conductor includes a plurality of magnetic sensors. In some embodiments, the sensors are grouped in pairs to achieve common mode rejection of signals generated in response to magnetic fields not resulting from current flow through the conductor. Sensors having different levels of sensitivity are used to collect information regarding the magnetic field generated by the current flowing through the conductor, where such information is processed in order to characterize the magnetic field. In some cases the sensors are included on or in flexible material that can be wrapped around the conductor.

    Circuit for wordline autobooting in memory and method therefor
    33.
    发明授权
    Circuit for wordline autobooting in memory and method therefor 有权

    公开(公告)号：US10573365B2

    公开(公告)日：2020-02-25

    申请号：US16251882

    申请日：2019-01-18

    Applicant: Everspin Technologies, Inc.

    Inventor： Thomas Andre ,  Syed M. Alam

    IPC: G11C11/16 ,  G06F11/10 ,  G11C11/4094 ,  G11C7/12 ,  G11C8/08 ,  G11C8/14

    Abstract: In a spin-torque magnetic random access memory (MRAM) that includes local source lines, auto-booting of the word line is used to reduce power consumption by reusing charge already present from driving a plurality of bit lines during writing operations. Auto-booting is accomplished by first driving a global word line to a first voltage. Driving the global word line to a first voltage results in a second voltage passed to the word lines. Subsequent driving of the plurality of bit lines that are capacitively coupled to the word line causes the word line voltage to be increased to a level desired to allow sufficient current to flow through a selected memory cell to write information into the selected memory cell.

    Self-referenced sense amplifier with precharge
    36.
    发明授权
    Self-referenced sense amplifier with precharge 有权

    公开(公告)号：US10475497B2

    公开(公告)日：2019-11-12

    申请号：US16000071

    申请日：2018-06-05

    Applicant: EVERSPIN TECHNOLOGIES, INC.

    Inventor： Syed M. Alam ,  Chitra Subramanian

    IPC: G11C11/00 ,  G11C11/16 ,  G11C27/02

    Abstract: Precharging circuits and techniques are presented for use with magnetic memory devices in order to speed up access to the memory cells for reading and writing. Including precharging in the sense amplifiers used to access the memory cells enables self-referenced read operations to be completed more quickly than is possible without precharging. Similarly, precharging can also be used in conjunction with write-back operations in order to allow the data state stored by magnetic tunnel junctions included in the memory cells to be changed more rapidly.

    Magnetoresistive stack/structure and method of manufacturing same
    37.
    发明授权
    Magnetoresistive stack/structure and method of manufacturing same 有权

    公开(公告)号：US10461250B2

    公开(公告)日：2019-10-29

    申请号：US16050749

    申请日：2018-07-31

    Applicant: Everspin Technologies, Inc.

    Inventor： Sarin A. Deshpande ,  Kerry Joseph Nagel ,  Chaitanya Mudivarthi ,  Sanjeev Aggarwal

    IPC: H01L43/12 ,  H01L43/08

    Abstract: A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer, (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.

    Two bit error correction via a field programmable gate array
    39.
    发明授权
    Two bit error correction via a field programmable gate array 有权

    公开(公告)号：US10348333B2

    公开(公告)日：2019-07-09

    申请号：US15711877

    申请日：2017-09-21

    Applicant: EVERSPIN TECHNOLOGIES, INC.

    Inventor： Kurt Baty

    IPC: H03M13/29 ,  G11C29/52 ,  G06F11/10 ,  H03M13/05

    Abstract: Apparatus, methods, and systems are disclosed for performing bit error correction on a data stream. In some aspects, the described systems and methods may include a plurality of memory devices, a first interface, and a field programmable gate array. The field programmable gate array may include a memory controller and a plurality of re-programmable gates. At least one of the re-programmable gates may be configured as a read-only memory (ROM) to store a syndrome decode memory table, wherein the syndrome decode memory table may be configured to perform bit error correction on the data stream being read and/or written to at least one memory device of the plurality of memory devices via the first interface.

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