公开(公告)号：US09679627B2

公开(公告)日：2017-06-13

申请号：US14502367

申请日：2014-09-30

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Dimitri Houssameddine ,  Syed M. Alam ,  Jon Slaughter ,  Chitra Subramanian

IPC: G11C16/04 ,  G11C11/16 ,  G06F12/0804

CPC classification number: G11C11/1675 ,  G06F12/0804 ,  G11C11/1677 ,  Y02D10/13

Abstract: A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.

公开(公告)号：US20160307615A1

公开(公告)日：2016-10-20

申请号：US15193010

申请日：2016-06-25

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam ,  Chitra Subramanian

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C7/02 ,  G11C7/065 ,  G11C11/16 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2013/0057 ,  G11C2207/002

Abstract: Self-referenced reading of a memory cell in a memory includes first applying a read voltage across the memory cell to produce a sample voltage. After applying the read voltage, a write current is applied to the memory cell to write a first state to the memory cell. After applying the write current, the read voltage is reapplied across the memory cell. An offset current is also applied while the read voltage is reapplied, and the resulting evaluation voltage from reapplying the read voltage with the offset current is compared with the sample voltage to determine the state of the memory cell.

Abstract translation: 存储器单元的自参考读取包括首先在存储器单元上施加读取电压以产生采样电压。 在施加读取电压之后，将写入电流施加到存储器单元以将第一状态写入存储单元。 在施加写入电流之后，读取电压被重新应用于存储器单元。 在重新施加读取电压的同时施加偏置电流，并将得到的评估电压与读取电压重新应用偏移电流相比较，以确定存储单元的状态。

公开(公告)号：US20160099040A1

公开(公告)日：2016-04-07

申请号：US14970564

申请日：2015-12-16

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam ,  Chitra Subramanian

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C7/02 ,  G11C7/065 ,  G11C11/16 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2013/0057 ,  G11C2207/002

Abstract: Circuitry and a method provide a plurality of timed control and bias voltages to sense amplifiers and write drivers of a spin-torque magnetoresistive random access memory array for improved power supply noise rejection, increased sensing speed with immunity for bank-to-bank noise coupling, and reduced leakage from off word line select devices in an active column.

公开(公告)号：US08923041B2

公开(公告)日：2014-12-30

申请号：US13835426

申请日：2013-03-15

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam ,  Chitra Subramanian

IPC: G11C11/00 ,  G11C11/16 ,  G11C7/02 ,  G11C13/00

CPC classification number: G11C11/1675 ,  G11C7/02 ,  G11C7/065 ,  G11C11/16 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2013/0057 ,  G11C2207/002

Abstract: Circuitry and a method provide a plurality of timed control and bias voltages to sense amplifiers and write drivers of a spin-torque magnetoresistive random access memory array for improved power supply noise rejection, increased sensing speed with immunity for bank-to-bank noise coupling, and reduced leakage from off word line select devices in an active column.

Abstract translation: 电路和方法提供多个定时控制和偏置电压来读取自旋转矩磁阻随机存取存储器阵列的放大器和写入驱动器，以改善电源噪声抑制，增加用于存储体间隔离噪声耦合的抗扰度的感测速度， 并减少活动列中的字线选择器件的泄漏。

公开(公告)号：US20180267899A1

公开(公告)日：2018-09-20

申请号：US15986167

申请日：2018-05-22

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam ,  Chitra Subramanian ,  Javed S. Barkatullah

IPC: G06F12/0893 ,  G06F3/06 ,  G11C7/10 ,  G06F12/0802 ,  G11C11/16 ,  G11C16/32 ,  G11C7/22 ,  G06F12/0862

CPC classification number: G06F12/0893 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0683 ,  G06F12/0215 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0851 ,  G06F12/0855 ,  G06F12/0862 ,  G06F2212/1024 ,  G06F2212/2024 ,  G06F2212/3042 ,  G06F2212/6026 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/22 ,  G11C11/1693 ,  G11C16/32 ,  G11C2207/2245 ,  G11C2207/2272 ,  Y02D10/13

Abstract: A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.

公开(公告)号：US09697880B2

公开(公告)日：2017-07-04

申请号：US15193010

申请日：2016-06-25

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam ,  Chitra Subramanian

IPC: G11C11/16 ,  G11C7/02 ,  G11C13/00

CPC classification number: G11C11/1675 ,  G11C7/02 ,  G11C7/065 ,  G11C11/16 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2013/0057 ,  G11C2207/002

Abstract: Self-referenced reading of a memory cell in a memory includes first applying a read voltage across the memory cell to produce a sample voltage. After applying the read voltage, a write current is applied to the memory cell to write a first state to the memory cell. After applying the write current, the read voltage is reapplied across the memory cell. An offset current is also applied while the read voltage is reapplied, and the resulting evaluation voltage from reapplying the read voltage with the offset current is compared with the sample voltage to determine the state of the memory cell.

公开(公告)号：US09245611B2

公开(公告)日：2016-01-26

申请号：US14702828

申请日：2015-05-04

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre ,  Matthew R. Croft ,  Chitra Subramanian ,  Halbert Lin

IPC: G11C11/00 ,  G11C11/16 ,  G06F11/10 ,  G11C29/04 ,  G11C13/00

CPC classification number: G11C11/1675 ,  G06F11/1048 ,  G06F11/1076 ,  G11C11/00 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2013/0076 ,  G11C2029/0411

Abstract: A method includes sampling magnetic bits, applying a write current pulse to the magnetic bits to set them to a first logic state, resampling the magnetic bits, and comparing the results of sampling and resampling to determine the bit state for each magnetic bit. A read or write operation may be received after initiation of writing back magnetic bits having the second state, where the write-back can be aborted for a portion of the bits in the case of a write operation. The write-back may be performed such that different portions of the magnetic bits are written back at different times, thereby staggering the write-back current pulses in time. An offset current may also be used during resampling.

Abstract translation: 一种方法包括采样磁头，将写入电流脉冲施加到磁性位以将其设置为第一逻辑状态，重新采样磁头，以及比较采样和重采样的结果，以确定每个磁性位的位状态。 在开始写入具有第二状态的磁性位之后可以接收读取或写入操作，其中在写入操作的情况下可以针对位的一部分中止回写。 可以执行回写，使得磁头的不同部分在不同的时间被写回，从而及时地交错回写电流脉冲。 在重采样期间也可以使用偏移电流。

公开(公告)号：US20150243337A1

公开(公告)日：2015-08-27

申请号：US14702828

申请日：2015-05-04

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre ,  Matthew R. Croft ,  Chitra Subramanian ,  Halbert Lin

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G06F11/1048 ,  G06F11/1076 ,  G11C11/00 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2013/0076 ,  G11C2029/0411

Abstract: A method includes sampling magnetic bits, applying a write current pulse to the magnetic bits to set them to a first logic state, resampling the magnetic bits, and comparing the results of sampling and resampling to determine the bit state for each magnetic bit. A read or write operation may be received after initiation of writing back magnetic bits having the second state, where the write-back can be aborted for a portion of the bits in the case of a write operation. The write-back may be performed such that different portions of the magnetic bits are written back at different times, thereby staggering the write-back current pulses in time. An offset current may also be used during resampling.

Abstract translation: 一种方法包括采样磁头，将写入电流脉冲施加到磁性位以将其设置为第一逻辑状态，重新采样磁头，以及比较采样和重采样的结果，以确定每个磁性位的位状态。 在开始写入具有第二状态的磁性位之后可以接收读取或写入操作，其中在写入操作的情况下可以针对位的一部分中止回写。 可以执行回写，使得磁头的不同部分在不同的时间被写回，从而及时地交错回写电流脉冲。 在重采样期间也可以使用偏移电流。

公开(公告)号：US20150029786A1

公开(公告)日：2015-01-29

申请号：US14494180

申请日：2014-09-23

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam ,  Chitra Subramanian

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C7/02 ,  G11C7/065 ,  G11C11/16 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2013/0057 ,  G11C2207/002

Abstract: Circuitry and a method provide a plurality of timed control and bias voltages to sense amplifiers and write drivers of a spin-torque magnetoresistive random access memory array for improved power supply noise rejection, increased sensing speed with immunity for bank-to-bank noise coupling, and reduced leakage from off word line select devices in an active column.

Abstract translation: 电路和方法提供多个定时控制和偏置电压来读取自旋转矩磁阻随机存取存储器阵列的放大器和写入驱动器，以改善电源噪声抑制，增加用于存储体到存储体噪声耦合的抗扰度的感测速度， 并减少活动列中的字线选择器件的泄漏。

公开(公告)号：US10475497B2

公开(公告)日：2019-11-12

申请号：US16000071

申请日：2018-06-05

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Syed M. Alam ,  Chitra Subramanian

IPC: G11C11/00 ,  G11C11/16 ,  G11C27/02

Abstract: Precharging circuits and techniques are presented for use with magnetic memory devices in order to speed up access to the memory cells for reading and writing. Including precharging in the sense amplifiers used to access the memory cells enables self-referenced read operations to be completed more quickly than is possible without precharging. Similarly, precharging can also be used in conjunction with write-back operations in order to allow the data state stored by magnetic tunnel junctions included in the memory cells to be changed more rapidly.