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公开(公告)号：US10027330B1
公开(公告)日：2018-07-17
申请号：US15889740
申请日：2018-02-06
Applicant: FARADAY TECHNOLOGY CORPORATION
Inventor： Zhao-Yong Zhang , Shih-Chin Lin , Wei-Chang Wang
Abstract: An arbitrating circuit includes a first NOR gate, a second NOR gate, four resistors and a pull-up circuit. The first transistor is connected with the first node and the second node, and generates a first acknowledging signal. The second transistor is connected with a supply voltage, the second node and the first transistor. The third transistor is connected with the first node and second node, and generates a second acknowledging signal. The fourth transistor is connected with the supply voltage, the first node and the third transistor. The pull-up circuit is connected with the first node, the second node, the first NOR gate and the second NOR gate. If both of the first request signal and the second request signal have a low logic level, a voltage at the second node is pulled up to a high logic level by the pull-up circuit.
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公开(公告)号：US09806923B2
公开(公告)日：2017-10-31
申请号：US15241618
申请日：2016-08-19
Applicant: FARADAY TECHNOLOGY CORPORATION
Inventor： Yuan-Min Hu , Jhen-Yu Hou
CPC classification number: H04L27/0014 , H03K3/00 , H03K5/1252 , H03L7/00 , H03L7/08 , H04J3/04 , H04L2027/0036
Abstract: A RXLOS deglitch apparatus for a receiver is provided. The RXLOS deglitch apparatus includes a sampler, an edge detecting unit and a finite state machine. The sampler receives a recovered clock, and samples a RXLOS signal according to the recovered clock. Consequently, a sampled RXLOS signal is generated. The edge detecting unit receives the RXLOS signal. When a logic level of the RXLOS signal is changed, an edge detection signal is activated by the edge detecting unit. The finite state machine receives the edge detection signal and the sampled RXLOS signal, generates an edge rest signal to control the edge detecting unit, and outputs a filtered RXLOS signal.
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公开(公告)号：US09753515B2
公开(公告)日：2017-09-05
申请号：US15081141
申请日：2016-03-25
Applicant: FARADAY TECHNOLOGY CORPORATION
Inventor： Chi-Yang Chen
Abstract: A power system includes a voltage regulating system and a digital circuit. The voltage regulating system receives a power down signal. The voltage regulating system selectively generates an output voltage according to the power down signal. When the digital circuit receives the output voltage, the digital circuit is operated. When the digital circuit is not operated, the power down signal is activated. After the external voltage source is switched on and before a voltage of the external voltage source reaches a fixed voltage, the voltage regulating system ignores the power down signal and generates the output voltage. After the voltage of the external voltage source reaches the fixed voltage, the voltage regulating system generates the output voltage if the power down signal is inactivated; the voltage regulating system stops generating the output voltage if the power down signal is activated.
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公开(公告)号：US20170133930A1
公开(公告)日：2017-05-11
申请号：US15081141
申请日：2016-03-25
Applicant: FARADAY TECHNOLOGY CORPORATION
Inventor： Chi-Yang Chen
Abstract: A power system includes a voltage regulating system and a digital circuit. The voltage regulating system receives a power down signal. The voltage regulating system selectively generates an output voltage according to the power down signal. When the digital circuit receives the output voltage, the digital circuit is operated. When the digital circuit is not operated, the power down signal is activated. After the external voltage source is switched on and before a voltage of the external voltage source reaches a fixed voltage, the voltage regulating system ignores the power down signal and generates the output voltage. After the voltage of the external voltage source reaches the fixed voltage, the voltage regulating system generates the output voltage if the power down signal is inactivated; the voltage regulating system stops generating the output voltage if the power down signal is activated.
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公开(公告)号：US20150325275A1
公开(公告)日：2015-11-12
申请号：US14492687
申请日：2014-09-22
Applicant: FARADAY TECHNOLOGY CORPORATION
Inventor： Hao Wu , Song-Wen Yang , Zhao-Yong Zhang , Kun-Ti Lee
IPC: G11C8/08
CPC classification number: G11C8/08 , G11C5/145 , G11C5/147 , G11C29/028 , G11C2029/1202
Abstract: A memory includes a logic controller, a word line driver, a boost circuit, plural capacitor circuits, plural memory cores, plural selectors, and plural output drivers. The logic controller generates a word line enabling signal and a boost enabling signal. The word line driver receives the word line enabling signal. The boost circuit receives the boost enabling signal. The plural capacitor circuits are connected between the boost circuit and the word line driver. Each of the plural memory cores is connected with the word line driver through plural word lines. The plural selectors are connected with the corresponding memory cores. The plural output drivers are connected with the corresponding selectors. The number of the plural memory cores is positively correlated with the number of the plural capacitor circuits.
Abstract translation: 存储器包括逻辑控制器，字线驱动器，升压电路，多个电容器电路，多个存储器核，多个选择器和多个输出驱动器。 逻辑控制器产生字线使能信号和升压使能信号。 字线驱动器接收字线使能信号。 升压电路接收升压使能信号。 多个电容电路连接在升压电路和字线驱动器之间。 多个存储器核心中的每一个通过多个字线与字线驱动器连接。 多个选择器与相应的存储器核心连接。 多个输出驱动器与相应的选择器连接。 多个存储器核的数量与多个电容器电路的数量正相关。
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Patent Agency Ranking
公开(公告)号：US09177624B1
公开(公告)日：2015-11-03
申请号：US14492687
申请日：2014-09-22
Applicant: FARADAY TECHNOLOGY CORPORATION
Inventor： Hao Wu , Song-Wen Yang , Zhao-Yong Zhang , Kun-Ti Lee
CPC classification number: G11C8/08 , G11C5/145 , G11C5/147 , G11C29/028 , G11C2029/1202
Abstract: A memory includes a logic controller, a word line driver, a boost circuit, plural capacitor circuits, plural memory cores, plural selectors, and plural output drivers. The logic controller generates a word line enabling signal and a boost enabling signal. The word line driver receives the word line enabling signal. The boost circuit receives the boost enabling signal. The plural capacitor circuits are connected between the boost circuit and the word line driver. Each of the plural memory cores is connected with the word line driver through plural word lines. The plural selectors are connected with the corresponding memory cores. The plural output drivers are connected with the corresponding selectors. The number of the plural memory cores is positively correlated with the number of the plural capacitor circuits.
Abstract translation: 存储器包括逻辑控制器，字线驱动器，升压电路，多个电容器电路，多个存储器核，多个选择器和多个输出驱动器。 逻辑控制器产生字线使能信号和升压使能信号。 字线驱动器接收字线使能信号。 升压电路接收升压使能信号。 多个电容电路连接在升压电路和字线驱动器之间。 多个存储器核心中的每一个通过多个字线与字线驱动器连接。 多个选择器与相应的存储器核心连接。 多个输出驱动器与相应的选择器连接。 多个存储器核的数量与多个电容器电路的数量正相关。
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公开(公告)号：US20240330225A1
公开(公告)日：2024-10-03
申请号：US18432412
申请日：2024-02-05
Applicant: FARADAY TECHNOLOGY CORPORATION
Inventor： Chun-Yuan LAI
IPC: G06F13/40
CPC classification number: G06F13/4068
Abstract: A physical layer module and a network module are provided. The network module includes the physical layer module and a media access control module. The physical layer module includes a group decoder, an input selection module, and a device module. The group decoder decodes a common input data signal generated according to a management data input/output signal to generate a group selection signal. The input selection module includes X input circuits being classified into M groups. The X input circuits generate X device input data according to the common input data signal and the group selection signal. The device module includes K physical layer devices classified into M groups. The K physical devices receive X device input data from the X input circuits. An m-th group corresponds to at least one input circuit and N[m] physical layer devices.
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公开(公告)号：US20240129213A1
公开(公告)日：2024-04-18
申请号：US18195961
申请日：2023-05-11
Applicant: FARADAY TECHNOLOGY CORPORATION
Inventor： Po-Hsuan LEE , I-Chuan CHIU , Shih-Yi SHIH
IPC: H04L43/0811 , H04L43/067
CPC classification number: H04L43/0811 , H04L43/067
Abstract: A link down detector and a link down detecting method for Ethernet are provided. The link down detecting method includes the following steps. Firstly, a received signal is received, and a high-frequency band signal is extracted from the received signal. Consequently, the high-frequency band signal is formed as an extraction signal. Then, a high-frequency band power value of the extraction signal is calculated, and a full band power value of the received signal is calculated. Then, a ratio value of the high-frequency band power value to the full band power value is calculated. In a link up status, if the ratio value is changed dramatically in a specified time, a link down signal is asserted to indicate that a network device connected to the Ethernet is switched to a link down status.
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公开(公告)号：US11775003B2
公开(公告)日：2023-10-03
申请号：US17565503
申请日：2021-12-30
Applicant: FARADAY TECHNOLOGY CORPORATION
Inventor： Vinod Kumar Jain , Chi-Yeu Chao
Abstract: A clock calibration module, a high-speed receiver, and an associated calibration method are provided. The calibration method is applied to the high-speed receiver having the clock calibration module and a sampler. The sampler samples an equalized data signal with a sampler-input clock. The clock calibration module includes multiple clock generation circuits and a clock calibration circuit. Each of the clock generation circuits includes a phase interpolator, a duty cycle corrector, and a phase corrector. In a calibration mode, the phase interpolator interpolates a reference input clock and generates an interpolated clock accordingly. The duty cycle corrector generates a duty cycle corrected clock based on the interpolated clock. The phase corrector generates the sampler-input clock based on the duty cycle corrected clock. The phase interpolator is controlled by a phase interpolator calibration signal, and the phase corrector is controlled by a phase corrector calibration signal.
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公开(公告)号：US20230299762A1
公开(公告)日：2023-09-21
申请号：US17694727
申请日：2022-03-15
Applicant: FARADAY TECHNOLOGY CORPORATION
Inventor： Hussainvali SHAIK , Sridhar CHERUKU , Sivaramakrishnan SUBRAMANIAN
IPC: H03K17/081 , H03K17/041
CPC classification number: H03K17/08104 , H03K17/04106
Abstract: A level shifter and an electronic device are provided. The electronic device includes a digital circuit and a level shifter. The level shifter converts a first and a second input signals to an output signal. The level shifter includes a cross-coupled circuit, a protection circuit, and a pull-down module. The cross-coupled circuit includes a first and a second pull-up transistors. The protection circuit includes a first and a second protection transistors. The pull-down module includes a first and a second pull-down circuits and a first and a second switching circuits. The first and the second pull-up transistors, the first and the second protection transistors, and the first and the second pull-down circuits are selectively switched on in response to the first and the second input signals. The digital circuit receives the output signal from the level shifter.
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