公开(公告)号：US5525551A

公开(公告)日：1996-06-11

申请号：US255727

申请日：1994-06-07

Applicant: Hiroyuki Ohta

Inventor： Hiroyuki Ohta

IPC: H01L21/316 ,  H01L21/318 ,  H01L21/205

CPC classification number: H01L21/02164 ,  H01L21/02271 ,  H01L21/02312 ,  H01L21/31608

Abstract: The present invention relates to a method for forming a silicon oxide film on a substrate by the thermal chemical vapor deposition method (thermal CVD method) using a gas mixture of ozone (O.sub.3) and tetraethoxyorthosilicate (TEOS). It is an object of the present invention to provide a method for forming an insulating film in a semiconductor device, in which anomalous deposition of the film at a step portion (a portion of difference in level) is prevented and the film contains less moisture and less organic matter and is superior in smoothness. The present invention includes the steps of exposing the depositing surface of the substrate 14 to tetraethoxyorthosilicate in the absence of oxygen and ozone at the elevated temperature and forming an oxide film 15 on the substrate 14 by the thermal CVD method using a gas mixture of ozone (O.sub.3) and tetraethoxyorthosilicate at a deposition temperature. In a second embodiment HMDS is substituted for TEOS in the pretreatment step.

Abstract translation: 本发明涉及使用臭氧（O3）和原硅酸四乙酯（TEOS）的气体混合物的热化学气相沉积法（热CVD法）在基板上形成氧化硅膜的方法。 本发明的目的是提供一种在半导体器件中形成绝缘膜的方法，其中防止了膜在步骤部分处的异常沉积（水平差异的一部分），并且膜含有较少的水分和 有机质少，平滑度优越。 本发明包括以下步骤：在升高的温度下，在不存在氧和臭氧的情况下将基材14的沉积表面暴露于原硅酸四乙酯，并且通过使用臭氧气体混合物的热CVD方法在基板14上形成氧化膜15 O3）和原硅酸四乙酯。 在第二实施方案中，HMDS在预处理步骤中代替TEOS。

公开(公告)号：US4822441A

公开(公告)日：1989-04-18

申请号：US198230

申请日：1988-05-25

Applicant: Hiroyuki Ohta ,  Naoki Yoshida ,  Hideo Goto

Inventor： Hiroyuki Ohta ,  Naoki Yoshida ,  Hideo Goto

IPC: H01L21/00 ,  B44C1/22 ,  B29C37/00 ,  C03C15/00 ,  C03C25/06

CPC classification number: H01L21/67126 ,  Y10T74/20912

Abstract: The plastic mold decapsuling apparatus comprises an etchant bottle; a heat tank; an etchant reservoir disposed in the heat tank; at least one decapsuling plastic mold holder; a first etchant feeding pump for selectively circulating the etchant from the etchant bottle to the etchant reservoir and discharging waste etchant; and a second etchant feeding pump for feeding the etchant from the reservoir to the plastic mold holder. Since the etchant bottle can be set as it is without transferring the etchant into another vessel, the etchant handling work is safe. Since a required amount of etchant can previously be heated in a reservoir within the heat tank, it is possible to continuously supply a predetermined amount of etchant heated to a constant temperature, thus improving the speed of decapsuling work. Futher, since the etchant is circulated through the decapsuling plastic mold holder, it is possible to firmly decapsule plastic mold devices by use of a relatively mild etchant such as fuming nitric acid.

Abstract translation: 塑料模具拆封装置包括蚀刻剂瓶; 加热箱 设置在所述加热罐中的蚀刻剂储存器; 至少一个开封塑料模架; 用于选择性地将蚀刻剂从蚀刻剂瓶循环到蚀刻剂储存器并排出废蚀刻剂的第一蚀刻剂进料泵; 以及用于将蚀刻剂从储存器供给到塑料模具保持器的第二蚀刻剂进料泵。 由于蚀刻剂瓶可以原样设置而不将蚀刻剂转移到另一个容器中，所以蚀刻剂处理工作是安全的。 由于可以预先在加热箱内的储存器中加热所需量的蚀刻剂，所以可以连续地供给加热到恒定温度的预定量的蚀刻剂，从而提高解封装工作的速度。 更重要的是，由于蚀刻液通过解封装的塑料模具支架循环，因此可以通过使用相对温和的蚀刻剂（例如发烟硝酸）来使塑料模具装置牢固地脱模。

公开(公告)号：US20120329229A1

公开(公告)日：2012-12-27

申请号：US13603577

申请日：2012-09-05

Applicant: Yosuke Shimamune ,  Masahiro Fukuda ,  Young Suk Kim ,  Akira Katakami ,  Akiyoshi Hatada ,  Naoyoshi Tamura ,  Hiroyuki Ohta

Inventor： Yosuke Shimamune ,  Masahiro Fukuda ,  Young Suk Kim ,  Akira Katakami ,  Akiyoshi Hatada ,  Naoyoshi Tamura ,  Hiroyuki Ohta

IPC: H01L21/336

CPC classification number: H01L29/7848 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

Abstract: A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of the first SiGe mixed crystal layer from the bottom of the trench is lower than the depth of the trench with the surface of the silicon substrate being the standard. The height of an uppermost surface of the second SiGe mixed crystal layer from the bottom of the trench is higher than the depth of the trench with the surface of the silicon substrate being the standard. Ge concentrations in the first and third SiGe mixed crystal layers are lower than a Ge concentration in the second SiGe mixed crystal layer.

公开(公告)号：US08324040B2

公开(公告)日：2012-12-04

申请号：US12785016

申请日：2010-05-21

Applicant: Hiroyuki Ohta

Inventor： Hiroyuki Ohta

IPC: H01L21/8238 ,  H01L21/44

CPC classification number: H01L29/7843 ,  H01L21/823412 ,  H01L21/823443 ,  H01L21/823456 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/82385 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: A semiconductor device including an n-channel MISFET including source/drain regions 38 formed in a semiconductor substrate 10 with a channel region between them, and a gate electrode 44 of a metal silicide formed over the channel region with a gate insulating film 12 interposed therebetween; and an insulating film 46 formed over the gate electrode 44 from side walls of the gate electrode 44 to an upper surface of the gate electrode 44, having a tensile stress from 1.0 to 2.0 GPa and applying the tensile stress to the channel region.

Abstract translation: 一种半导体器件，包括n沟道MISFET，其包括形成在半导体衬底10中的沟道区域之间的源极/漏极区域38和在沟道区域上形成的金属硅化物的栅电极44，栅极绝缘膜12插入其间 ; 以及从栅电极44的侧壁到栅电极44的上表面的栅电极44的上方形成的绝缘膜46，拉伸应力为1.0〜2.0GPa，并对该沟道区施加拉伸应力。

公开(公告)号：US07906848B2

公开(公告)日：2011-03-15

申请号：US12389071

申请日：2009-02-19

Applicant: Yukihiro Kumagai ,  Hiroyuki Ohta ,  Naotaka Tanaka ,  Masahiko Fujisawa ,  Akihiko Ohsaki

Inventor： Yukihiro Kumagai ,  Hiroyuki Ohta ,  Naotaka Tanaka ,  Masahiko Fujisawa ,  Akihiko Ohsaki

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L23/53238 ,  H01L23/3128 ,  H01L23/53295 ,  H01L23/585 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2224/0401

Abstract: In a semiconductor device having a Low-k film as an interlayer insulator, peeling of the interlayer insulator in a thermal cycle test is prevented, thereby providing a highly reliable semiconductor device. In a semiconductor device having a structure in which interlayer insulators in which buried wires each having a main electric conductive layer made of copper are formed and cap insulators of the buried wires are stacked, the cap insulator having a relatively high Young's modulus and contacting by its upper surface with the interlayer insulator made of a Low-k film having a relatively low Young's modulus is formed so as not to be provided in an edge portion of the semiconductor device.

Abstract translation: 在具有Low-k膜作为层间绝缘体的半导体器件中，防止了热循环试验中的层间绝缘体的剥离，从而提供高可靠性的半导体器件。 在具有这样的结构的半导体器件中，其中形成有由铜制成的主导电层的埋入布线和层叠埋入导线的帽绝缘体的层间绝缘体，所述盖绝缘体具有较高的杨氏模量并且通过其接触 形成具有相对低的杨氏模量的由Low-k膜制成的层间绝缘体的上表面，以便不设置在半导体器件的边缘部分中。

公开(公告)号：US07906798B2

公开(公告)日：2011-03-15

申请号：US11950102

申请日：2007-12-04

Applicant: Hiroyuki Ohta ,  Katsuaki Ookoshi

Inventor： Hiroyuki Ohta ,  Katsuaki Ookoshi

IPC: H01L27/092

CPC classification number: H01L21/823864 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

Abstract: A semiconductor device includes an NMOS transistor and a PMOS transistor. The NMOS transistor includes a channel area formed in a silicon substrate, a gate electrode formed on a gate insulating film in correspondence with the channel area, and a source area and a drain area formed in the silicon substrate having the channel area situated therebetween. The PMOS transistor includes another channel area formed in the silicon substrate, another gate electrode formed on another gate insulating film in correspondence with the other channel area, and another source area and another drain area formed in the silicon substrate having the other channel area situated therebetween. The gate electrode has first sidewall insulating films. The other gate electrode has second sidewall insulating films. The distance between the second sidewall insulating films and the silicon substrate is greater than the distance between the first sidewall insulating films and the silicon substrate.

Abstract translation: 半导体器件包括NMOS晶体管和PMOS晶体管。 NMOS晶体管包括形成在硅衬底中的沟道区，形成在与沟道区相对应的栅极绝缘膜上的栅电极，以及形成在硅衬底中的沟道区的源极区和漏区，位于其间。 PMOS晶体管包括形成在硅衬底中的另一沟道区，与另一沟道区相对应的另一栅极电极上形成的另一栅电极，以及形成在硅衬底中的另一源极区和另一漏极区，其另一沟道区位于其间 。 栅电极具有第一侧壁绝缘膜。 另一个栅电极具有第二侧壁绝缘膜。 第二侧壁绝缘膜和硅衬底之间的距离大于第一侧壁绝缘膜和硅衬底之间的距离。

公开(公告)号：US20110049533A1

公开(公告)日：2011-03-03

申请号：US12916953

申请日：2010-11-01

Applicant: Yosuke Shimamune ,  Hiroyuki Ohta ,  Akiyoshi Hatada ,  Akira Katakami ,  Naoyoshi Tamura

Inventor： Yosuke Shimamune ,  Hiroyuki Ohta ,  Akiyoshi Hatada ,  Akira Katakami ,  Naoyoshi Tamura

IPC: H01L29/24

CPC classification number: H01L29/165 ,  H01L29/045 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.

Abstract translation: 公开了一种制造半导体器件的方法，其能够抑制短沟道效应并改善载流子迁移率。 在该方法中，在对应于源极区和漏极区的硅衬底中形成沟槽。 当外延生长p型半导体混晶层以填充沟槽时，沟槽的表面被刻面划分，半导体混晶层的延伸部分形成在第二侧壁绝缘膜的底表面和 硅衬底和延伸部分与源极延伸区域和漏极延伸区域接触。

公开(公告)号：US20100233860A1

公开(公告)日：2010-09-16

申请号：US12785016

申请日：2010-05-21

Applicant: Hiroyuki OHTA

Inventor： Hiroyuki OHTA

IPC: H01L21/8234

CPC classification number: H01L29/7843 ,  H01L21/823412 ,  H01L21/823443 ,  H01L21/823456 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/82385 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: A semiconductor device including an n-channel MISFET including source/drain regions 38 formed in a semiconductor substrate 10 with a channel region between them, and a gate electrode 44 of a metal silicide formed over the channel region with a gate insulating film 12 interposed therebetween; and an insulating film 46 formed over the gate electrode 44 from side walls of the gate electrode 44 to an upper surface of the gate electrode 44, having a tensile stress from 1.0 to 2.0 GPa and applying the tensile stress to the channel region.

Abstract translation: 一种半导体器件，包括n沟道MISFET，其包括形成在半导体衬底10中的沟道区域之间的源极/漏极区域38和在沟道区域上形成的金属硅化物的栅电极44，栅极绝缘膜12插入其间 ; 以及从栅电极44的侧壁到栅电极44的上表面的栅电极44的上方形成的绝缘膜46，拉伸应力为1.0〜2.0GPa，并对该沟道区施加拉伸应力。

公开(公告)号：US07793551B2

公开(公告)日：2010-09-14

申请号：US12184426

申请日：2008-08-01

Applicant: Hiromi Shimazu ,  Yohei Tanno ,  Hiroyuki Ohta ,  Ryuji Takada ,  Takayuki Shimodaira

Inventor： Hiromi Shimazu ,  Yohei Tanno ,  Hiroyuki Ohta ,  Ryuji Takada ,  Takayuki Shimodaira

IPC: G01B7/16

CPC classification number: G01L1/2225 ,  G01L1/18 ,  G01L1/26 ,  G01L5/162 ,  Y10T29/49103

Abstract: The invention provides a load sensor which is driven by a low electric power consumption, can measure at a high precision, and has a high reliability without being broken. The load sensor is structured such that a detection rod for detecting a strain is provided in an inner portion of a hole formed near a center of a pin via a shock relaxation material and a semiconductor strain sensor is provided in the detection rod, in a load sensor detecting a load applied to the pin from a strain generated in an inner portion of the pin.

Abstract translation: 本发明提供了一种由低功耗驱动的负载传感器，可以高精度地测量，并且具有高可靠性而不被破坏。 负载传感器被构造成使得用于检测应变的检测杆通过冲击松弛材料设置在靠近销的中心的孔的内部，并且半导体应变传感器设置在检测棒中，在负载 传感器检测从销的内部产生的应变施加到销的负载。

公开(公告)号：US07770462B2

公开(公告)日：2010-08-10

申请号：US12184104

申请日：2008-07-31

Applicant: Hiroyuki Ohta ,  Takashi Sumigawa

Inventor： Hiroyuki Ohta ,  Takashi Sumigawa

IPC: G01B7/06

CPC classification number: G01L1/18

Abstract: A mechanical quantity measuring apparatus is provided which can make highly precise measurements and is not easily affected by noise even when it is supplied an electricity through electromagnetic induction or microwaves. At least a strain sensor and an amplifier, an analog/digital converter, a rectification/detection/modulation-demodulation circuit, and a communication control circuit are formed in one and the same silicon substrate. Or, the silicon substrate is also formed at its surface with a dummy resistor which has its longitudinal direction set in a particular crystal orientation and which, together with the strain sensor, forms a Wheatstone bridge. With this arrangement, even when a current flowing through the sensor is reduced, measured data is prevented from being buried in noise, allowing the sensor to operate on a small power and to measure a mechanical quantity with high precision even when it is supplied electricity through electromagnetic induction or microwaves.

Abstract translation: 提供了能够进行高精度测量并且即使当通过电磁感应或微波供应电而不易受噪声影响的机械量测量装置。 至少一个应变传感器和放大器，模拟/数字转换器，整流/检测/调制解调电路和通信控制电路形成在同一个硅衬底中。 或者，硅衬底也在其表面上形成一个虚拟电阻器，该虚拟电阻器的纵向方向设置在特定的晶体取向中，并与应变传感器一起形成惠斯通电桥。 通过这种布置，即使当流过传感器的电流减小时，也可以防止测量数据被埋入噪声中，使得传感器能够以小功率工作，并且即使在通过电力供应通过时也以高精度测量机械量 电磁感应或微波。