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54 条记录 (耗时 0.021 秒)

    Method for selectively controlling damascene CD bias
    33.
    发明授权
    Method for selectively controlling damascene CD bias 失效
    选择性控制镶嵌CD偏压的方法

    公开(公告)号：US06972258B2

    公开(公告)日：2005-12-06

    申请号：US10634086

    申请日：2003-08-04

    申请人： Yin-Shen Chu ,  Hung-Ming Chen

    发明人： Yin-Shen Chu ,  Hung-Ming Chen

    IPC分类号： H01L21/311 ,  H01L21/44 ,  H01L21/461 ,  H01L21/4763 ,  H01L21/768

    CPC分类号： H01L21/76804 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76807

    摘要： A method for selectively etching a semiconductor feature opening to controllably achieve a critical dimension accuracy including providing a semiconductor wafer including a first opening formed extending through a thickness of at least one dielectric insulating layer and having an uppermost inorganic BARC layer; depositing a photoresist layer over the uppermost BARC layer and patterning the photoresist layer to form an etching pattern for etching a second opening overlying and encompassing the first opening; carrying out a first plasma assisted etching process to etch through a thickness of the BARC layer including a predetermined amount of CO in a plasma etching chemistry to increase an etching resistance of the photoresist layer; and, carrying out a second plasma assisted etching process to etch through a thickness portion of the at least one dielectric insulating layer to form the second opening.

    摘要翻译： 一种用于选择性蚀刻半导体特征开口以可控地实现临界尺寸精度的方法，包括提供半导体晶片，所述半导体晶片包括延伸穿过至少一个介电绝缘层的厚度并具有最上层的无机BARC层的第一开口; 在最上层的BARC层上沉积光致抗蚀剂层并图案化光致抗蚀剂层以形成用于蚀刻覆盖并包围第一开口的第二开口的蚀刻图案; 执行第一等离子体辅助蚀刻工艺以在等离子体蚀刻化学中蚀刻包括预定量的CO的BARC层的厚度，以增加光致抗蚀剂层的耐腐蚀性; 以及进行第二等离子体辅助蚀刻工艺以蚀刻通过所述至少一个介电绝缘层的厚度部分以形成所述第二开口。

    Rotating pin clasp apparatus
    34.
    发明申请
    Rotating pin clasp apparatus 失效
    旋转针扣装置

    公开(公告)号：US20050262667A1

    公开(公告)日：2005-12-01

    申请号：US10709817

    申请日：2004-05-30

    申请人： Chien-Jui Wang ,  Chia-Chuan Lin ,  Hung-ming Chen

    发明人： Chien-Jui Wang ,  Chia-Chuan Lin ,  Hung-ming Chen

    IPC分类号： A44B9/00 ,  A45F5/02

    CPC分类号： A45F5/02 ,  Y10T24/1365 ,  Y10T24/4657 ,  Y10T24/4661 ,  Y10T24/467 ,  Y10T24/4698

    摘要： A rotating pin clasp apparatus includes a base member with a cavity formed on the surface of the base member and a rod disposed in the cavity of the base member. The rod includes a recess and a pin utilized for fastening the rotating pin clasp apparatus, where a first end of the pin is rotatably attached to the rod at a pivot. The rod also includes a pin-retaining member for clasping a second end of the pin to the rod and a knob for rotating the rod in the cavity of the base member. A collar is formed on the base member and fitted around the recess of the rod for securing the rod to the base member and for permitting the rod to rotate in the cavity of the base member.

    摘要翻译： 旋转销扣式装置包括：基部构件，其具有形成在基部构件的表面上的空腔和设置在基座构件的空腔中的杆。 杆包括用于紧固旋转销扣式装置的凹部和销，其中销的第一端在枢轴处可旋转地附接到杆。 所述杆还包括用于将所述销的第二端紧固到所述杆的销保持构件和用于在所述基座构件的空腔中旋转所述杆的旋钮。 轴环形成在基座构件上并且围绕杆的凹部安装，用于将杆固定到基座构件上并允许杆在基座构件的空腔中旋转。

    Fin structure of fin field effect transistor
    37.
    发明授权
    Fin structure of fin field effect transistor 有权
    翅片场效应晶体管的鳍结构

    公开(公告)号：US09484462B2

    公开(公告)日：2016-11-01

    申请号：US12766233

    申请日：2010-04-23

    申请人： Feng Yuan ,  Hung-Ming Chen ,  Tsung-Lin Lee ,  Chang-Yun Chang ,  Clement Hsingjen Wann

    发明人： Feng Yuan ,  Hung-Ming Chen ,  Tsung-Lin Lee ,  Chang-Yun Chang ,  Clement Hsingjen Wann

    IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/66

    CPC分类号： H01L29/66795 ,  H01L21/308 ,  H01L29/7851 ,  H01L29/7853

    摘要： An exemplary structure for the fin field effect transistor comprises a substrate comprising a major surface; a plurality of fin structures protruding from the major surface of the substrate, wherein each fin structure comprises an upper portion and a lower portion separated at a transition location at where the sidewall of the fin structure is at an angle of 85 degrees to the major surface of the substrate, wherein the upper portion has sidewalls that are substantially perpendicular to the major surface of the substrate and a top surface having a first width, wherein the lower portion has tapered sidewalls on opposite sides of the upper portion and a base having a second width larger than the first width; and a plurality of isolation structures between the fin structures, wherein each isolation structure extends from the major surface of the substrate to a point above the transition location.

    摘要翻译： 鳍状场效应晶体管的示例性结构包括：包括主表面的衬底; 多个翅片结构，从所述基底的主表面突出，其中每个翅片结构包括在翅片结构的侧壁与主表面成85度角的过渡位置处分离的上部和下部 ，其中所述上部具有基本上垂直于所述基底的主表面的侧壁和具有第一宽度的顶表面，其中所述下部具有在所述上部的相对侧上的锥形侧壁和具有第二宽度的基部 宽度大于第一宽度; 以及在翅片结构之间的多个隔离结构，其中每个隔离结构从基板的主表面延伸到过渡位置上方的点。

    Silicide formation and associated devices
    38.
    发明授权
    Silicide formation and associated devices 有权
    硅化物形成和相关设备

    公开(公告)号：US08466027B2

    公开(公告)日：2013-06-18

    申请号：US13227979

    申请日：2011-09-08

    申请人： Hung-Ming Chen ,  Chih-Hao Chang ,  Chih-Hao Yu

    发明人： Hung-Ming Chen ,  Chih-Hao Chang ,  Chih-Hao Yu

    IPC分类号： H01L21/336

    CPC分类号： H01L29/785 ,  H01L21/823431 ,  H01L29/401 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7845

    摘要： Improved silicide formation and associated devices are disclosed. An exemplary method includes providing a semiconductor material having spaced source and drain regions therein, forming a gate structure interposed between the source and drain regions, performing a gate replacement process on the gate structure to form a metal gate electrode therein, forming a hard mask layer over the metal gate electrode, forming silicide layers on the respective source and drain regions in the semiconductor material, removing the hard mask layer to expose the metal gate electrode, and forming source and drain contacts, each source and drain contact being conductively coupled to a respective one of the silicide layers.

    摘要翻译： 公开了改进的硅化物形成和相关装置。 一种示例性方法包括提供其间具有间隔的源极和漏极区域的半导体材料，形成插入在源极和漏极区域之间的栅极结构，在栅极结构上执行栅极替换处理以在其中形成金属栅电极，形成硬掩模层 在所述金属栅极电极上，在所述半导体材料中的相应源极和漏极区域上形成硅化物层，去除所述硬掩模层以暴露所述金属栅电极，以及形成源极和漏极接触，每个源极和漏极接触导电耦合到 相应的一个硅化物层。

    CMOS Device with Raised Source and Drain Regions
    39.
    发明申请
    CMOS Device with Raised Source and Drain Regions 审中-公开
    CMOS器件具有引出源和漏极区域

    公开(公告)号：US20110298049A1

    公开(公告)日：2011-12-08

    申请号：US13210993

    申请日：2011-08-16

    申请人： Chun-Sheng Liang ,  Hung-Ming Chen ,  Chien-Chao Huang ,  Fu-Liang Yang

    发明人： Chun-Sheng Liang ,  Hung-Ming Chen ,  Chien-Chao Huang ,  Fu-Liang Yang

    IPC分类号： H01L27/092

    CPC分类号： H01L21/823814 ,  H01L27/092 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

    摘要： A semiconductor structure includes a semiconductor substrate comprising a PMOS region and an NMOS region; a PMOS device in the PMOS region; and an NMOS device in the NMOS region. The PMOS device includes a first gate stack on the semiconductor substrate; a first offset spacer on a sidewall of the first gate stack; a stressor in the semiconductor substrate and adjacent to the first offset spacer; and a first raised source/drain extension region on the stressor and adjoining the first offset spacer, wherein the first raised source/drain extension region has a higher p-type dopant concentration than the stressor. The NMOS device in the NMOS region includes a second gate stack on the semiconductor substrate; a second offset spacer on a sidewall of the second gate stack; a second raised source/drain extension region on the semiconductor substrate and adjoining the second offset spacer; and a deep source/drain region adjoining the second raised source/drain extension region, wherein the deep source/drain region is free from stressors formed in the semiconductor substrate.

    摘要翻译： 半导体结构包括：包括PMOS区域和NMOS区域的半导体衬底; PMOS区域中的PMOS器件; 和NMOS区域中的NMOS器件。 PMOS器件包括在半导体衬底上的第一栅叠层; 在所述第一栅极堆叠的侧壁上的第一偏移间隔物; 所述半导体衬底中的应力源并且与所述第一偏移间隔物相邻; 以及在所述应力器上并与所述第一偏移间隔物邻接的第一升高的源极/漏极延伸区域，其中所述第一升高的源极/漏极延伸区域具有比所述应力源更高的p型掺杂剂浓度。 NMOS区域中的NMOS器件包括在半导体衬底上的第二栅极堆叠; 在所述第二栅极堆叠的侧壁上的第二偏移间隔物; 在所述半导体衬底上的第二凸起的源极/漏极延伸区域，并邻接所述第二偏移间隔物; 以及与第二升高源极/漏极延伸区域相邻的深源极/漏极区域，其中深的源极/漏极区域没有形成在半导体衬底中的应力源。

    STI Shape Near Fin Bottom of Si Fin in Bulk FinFET
    40.
    发明申请
    STI Shape Near Fin Bottom of Si Fin in Bulk FinFET 有权
    在散装FinFET中的Si Fin附近的STI形状的STI形状

    公开(公告)号：US20110097889A1

    公开(公告)日：2011-04-28

    申请号：US12843693

    申请日：2010-07-26

    申请人： Feng Yuan ,  Tsung-Lin Lee ,  Hung-Ming Chen ,  Chang-Yun Chang

    发明人： Feng Yuan ,  Tsung-Lin Lee ,  Hung-Ming Chen ,  Chang-Yun Chang

    IPC分类号： H01L21/28

    CPC分类号： H01L21/845 ,  H01L21/76224 ,  H01L21/823431 ,  H01L29/66795

    摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate including a top surface; forming a first insulation region and a second insulation region in the semiconductor substrate; and recessing the first insulation region and the second insulation region. Top surfaces of remaining portions of the first insulation region and the second insulation region are flat surfaces or divot surfaces. A portion of the semiconductor substrate between and adjoining removed portions of the first insulation region and the second insulation region forms a fin.

    摘要翻译： 形成集成电路结构的方法包括提供包括顶表面的半导体衬底; 在所述半导体衬底中形成第一绝缘区域和第二绝缘区域; 并使第一绝缘区域和第二绝缘区域凹陷。 第一绝缘区域和第二绝缘区域的剩余部分的顶表面是平坦表面或表面。 第一绝缘区域和第二绝缘区域的相邻去除部分之间的半导体衬底的一部分形成翅片。