公开(公告)号：US10382083B2

公开(公告)日：2019-08-13

申请号：US16117608

申请日：2018-08-30

Applicant: Integrated Device Technology, Inc.

Inventor： Andrea Betti-Berutto ,  Sushil Kumar ,  Shawn Parker ,  Jonathan L. Kennedy ,  Christopher Saint ,  Michael Shaw ,  James Little ,  Jeff Illgner

IPC: H04B1/38 ,  H04B1/28 ,  H04B1/40 ,  H01L25/16 ,  H01L23/66 ,  H04B1/04 ,  H04B1/16 ,  H03F3/193 ,  H04W52/02 ,  H03F3/21 ,  H01L25/18 ,  H01L27/06

Abstract: An e-band transceiver includes a transmitter circuit and a receiver circuit. The transmitter circuit includes a surface mounted technology (SMT) module on which is mounted a silicon-germanium (SiGe) bipolar plus CMOS (BiCMOS) converter, a gallium arsenide (GaAs) pseudomorphic high-electron-mobility transistor (pHEMT) output amplifier coupled to the SiGe BiCMOS converter, and a microstrip/waveguide interface coupled to the GaAs pHEMT output amplifier. The receiver circuit of the e-band transceiver includes a receiver-side SMT module on which is mounted a receiver-side SiGe BiCMOS converter, a GaAs pHEMT low noise amplifier coupled to the receiver-side SiGe BiCMOS converter, and a receiver-side microstrip/waveguide interface coupled to the receiver-side GaAs pHEMT low noise amplifier.

公开(公告)号：US10367494B2

公开(公告)日：2019-07-30

申请号：US16155023

申请日：2018-10-09

Applicant: Integrated Device Technology, Inc.

Inventor： Xinqing Chen ,  HaiQi Liu ,  Yuan Zhang

IPC: H03K5/19 ,  H03K19/21 ,  G01R23/02

Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may be configured to generate a waveform in response to a frequency of an input clock signal and a threshold frequency. The second circuit may be configured to generate a control signal in response to a type of the waveform. The type of the waveform may comprise at least one of pulses and a steady state. The control signal may have a first state when the type of the waveform is the pulses and a second state when the type of the waveform is the steady state. A width of the pulses may be based on the threshold frequency.

公开(公告)号：US20190230523A1

公开(公告)日：2019-07-25

申请号：US16371633

申请日：2019-04-01

Applicant: Integrated Device Technology, Inc.

Inventor： Mohammad S. Akhter ,  John Bradley Deforge

IPC: H04W16/28 ,  H04B7/06 ,  H04W72/04

CPC classification number: H04W16/28 ,  H04B7/0408 ,  H04B7/0617 ,  H04W72/044 ,  H04W72/046 ,  H04W84/042

Abstract: An apparatus includes a transceiver circuit, an antenna and a focus array. The transceiver circuit may have a plurality of fed channels configured to generate a plurality of signals. The antenna may have a plurality of antenna arrays configured to generate one or more beams in response to the signals. Each antenna array may (i) have a plurality of subarrays and (ii) be coupled to the fed channels of the transceiver circuit. The focus array may have a plurality of focal zones configured to reflect the beams into a beam zone. Each beam may be steerable by the antenna to one of the focal zones at a time. The focal zones may redirect the beams to a plurality of locations within the beam zone.

公开(公告)号：US20190223128A1

公开(公告)日：2019-07-18

申请号：US16363116

申请日：2019-03-25

Applicant: Integrated Device Technology, Inc.

Inventor： Jagdeep Bal ,  Elie Ayache ,  Eduard Van Keulen

IPC: H04W56/00 ,  H04L7/04

CPC classification number: H04W56/0015 ,  H04L7/0008 ,  H04L7/04

Abstract: A system includes a first device comprising a first clock generating circuit and a transmitter circuit, and a plurality of second devices, each comprising a respective receiver circuit and a respective second clock generating circuit. The first clock generating circuit may be configured to generate a first clock signal, which may provide internal clocking for the first device. The transmitter circuit may be configured to generate a synchronization signal in response to the first clock signal and wirelessly transmit a broadcast signal communicating only the synchronization signal. The respective receiver circuit may be configured to receive the broadcast signal and present a recovered synchronization signal to the respective second clock generating circuit. The respective second clock generating circuit may be configured to generate a respective intermediate clock signal, synchronize the respective intermediate clock signal with the recovered synchronization signal, and generate a respective second clock signal that provides internal clocking for the second device.

公开(公告)号：US10355699B2

公开(公告)日：2019-07-16

申请号：US15833117

申请日：2017-12-06

Applicant: Integrated Device Technology, Inc.

Inventor： Menno Spijker

IPC: H03L7/07 ,  H03L7/08 ,  H03L7/093 ,  H03L7/099 ,  H03B5/04 ,  H03B5/32 ,  H04W88/08

Abstract: An apparatus comprising an accumulator circuit and an offset register. The accumulator circuit may be configured to (a) receive a plurality of frequency offset values from a plurality of sourcing DPLLs and (b) generate a current combined offset value in response to a sum of the frequency offset values. The offset register may be configured to (a) store an offset value corresponding to the current combined offset value in a first mode and (b) store an offset value corresponding to an updated offset value in a second mode. The updated offset value may comprise a difference between the offset value stored in the offset register and the current combined offset value. The offset value may be presented to a receiving DPLL during a re-arrangement of the sourcing DPLLs. Presenting the offset value may reduce a phase transient caused by the re-arrangement.

公开(公告)号：US20190187744A1

公开(公告)日：2019-06-20

申请号：US16194657

申请日：2018-11-19

Applicant: Integrated Device Technology, Inc.

Inventor： David Chang ,  Xudong Shi

IPC: G06F1/10 ,  G06F1/08 ,  G11C7/22 ,  H03K5/05 ,  H03L7/08 ,  G11C29/02 ,  G11C5/04 ,  G11C29/00 ,  G11C11/4096 ,  G11C11/4076 ,  G11C7/10

CPC classification number: G06F1/10 ,  G06F1/08 ,  G11C5/04 ,  G11C7/1039 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/00 ,  G11C29/023 ,  G11C29/028 ,  G11C29/1201 ,  G11C29/12015 ,  G11C2029/0403 ,  G11C2207/2254 ,  H03K5/05 ,  H03L7/08

Abstract: An apparatus includes a clock tree circuit, a first phase interpolator circuit and a second phase interpolator circuit. The clock tree circuit may be configured to generate a first clock delayed from a system clock by a constant time. The first phase interpolator circuit may be in a calibration loop and configured to generate a second clock with a programmable phase delay relative to the first clock. The programmable phase delay may be controlled by a control value. The calibration loop may be configured to determine the control value that results in a given delay between the system clock and the second clock. The second phase interpolator circuit may be in a normal signal path and configured to generate a third clock with the given delay relative to the first clock using the control value such that the third clock is offset from the system clock by the given delay.

公开(公告)号：US20190170584A1

公开(公告)日：2019-06-06

申请号：US16312985

申请日：2017-07-04

Applicant: Integrated Device Technology, Inc.

Inventor： Matthias GARZAROLLI ,  Thomas REICHEL

IPC: G01J3/51 ,  G01J3/02 ,  G02B5/28 ,  H01L27/146

CPC classification number: G01J3/513 ,  G01J3/0227 ,  G02B5/285 ,  G02B5/286 ,  H01L27/14621

Abstract: Embodiments of the invention relate to a method for producing a color sensor with a sensor characteristic adjusted by three sensor elements that each comprise an element characteristic, and a color filter cooperating with the sensor elements and consisting of color filter elements that each comprise a filter element characteristic, and to a color sensor. Embodiments include a method with which a color sensor with a precisely adjustable sensor characteristic can be produced from several photosensitive elements and from simple filter elements is solved in that the particular filter element characteristics are adjusted in such a manner that they have in cooperation with the respective element characteristic an interim characteristic of the sensor which deviates from the sensor characteristic on the whole, wherein the sensor characteristic is generated from the interim characteristic by a transformation algorithm using transformation parameters.

公开(公告)号：US10313565B2

公开(公告)日：2019-06-04

申请号：US14316329

申请日：2014-06-26

Applicant: Integrated Device Technology, Inc.

Inventor： Pavel Novotny ,  Eric Pearson

IPC: H04N1/409 ,  H04N5/14 ,  H04N21/2187

Abstract: A technique to perform edge-aware spatial noise filtering that may filter random noise from frames while maintaining the edges in the frames. The technique may include receiving a frame comprising a pint ht of pixels, filtering a subset of the plurality of pixels based on a weighting factor associated with each pixel of the subset of pixels, wherein the weighting factor is at least in part based on a difference in pixel value between the pixel and the individual pixels in the subset, and providing the filtered pixel to an encoder for encoding. Example implementation may include a spatial noise filter to receive an image, the noise level, and configuration parameters, and configured to determine weighting factors of pixels of the image based on differences in pixel values and a set of configuration parameters, and further configured to filter noise from the image based on the weighting factors of the pixels.

公开(公告)号：US20190158066A1

公开(公告)日：2019-05-23

申请号：US16196165

申请日：2018-11-20

Applicant: Integrated Device Technology, Inc.

Inventor： Hojung Ju ,  Roberto Aparicio Joo

IPC: H03H11/06 ,  H04B1/48 ,  H03H11/34

Abstract: An apparatus comprises a first RF port, a second RF port, a first resonator circuit and at least one second resonator circuit. The first resonator circuit and the second resonator circuit may be connected between the first RF port and the second RF port. The first resonator circuit may comprise a first inductor, a first capacitor, and a first stacked switch device. The second resonator circuit may comprise a second inductor, a second capacitor, and a second stacked switch device. The first capacitor and the first stacked switch device may be coupled in series across the first inductor. The second capacitor, the second inductor, and the second stacked switch device may be connected in parallel.

公开(公告)号：US20190131956A1

公开(公告)日：2019-05-02

申请号：US16167813

申请日：2018-10-23

Applicant: Integrated Device Technology, Inc.

Inventor： Shawn Bawell

IPC: H03H11/24 ,  H03H7/25 ,  H03G1/00

Abstract: An apparatus includes a bypass circuit a resistor circuit and multiple staggered circuits. The bypass circuit may have a predetermined number of a plurality of transistors connected in series between an input node and an output node. The resistor circuit may have a given number of resistors connected in series between the input node and the output node. Adjoining pairs of the resistors may be connected at given nodes. The staggered circuits may be connected between the given nodes and either the input node or the output node. Each staggered circuit may have a respective number of the transistors connected in series. The bypass circuit, the resistor circuit and the staggered circuits may form part of a bridge attenuator.