公开(公告)号：US20070177427A1

公开(公告)日：2007-08-02

申请号：US11698071

申请日：2007-01-26

Applicant: Geon-Woo Park ,  Geum-Jong Bae ,  In-Wook Cho ,  Byoung-Jin Lee ,  Myung-Yoon Um ,  Sang-Chul Lee

Inventor： Geon-Woo Park ,  Geum-Jong Bae ,  In-Wook Cho ,  Byoung-Jin Lee ,  Myung-Yoon Um ,  Sang-Chul Lee

IPC: G11C16/04

CPC classification number: G11C16/0425 ,  G11C16/04 ,  G11C16/0466 ,  G11C16/12 ,  G11C16/3418 ,  G11C16/3427 ,  G11C29/50 ,  G11C29/50004 ,  G11C2029/5002

Abstract: A nonvolatile memory device and method thereof are provided. The example method may include applying a first bias voltage to a gate electrode, applying a second bias voltage to a substrate to obtain a first voltage potential difference between the gate electrode and the substrate and applying a third bias voltage to a first impurity region to obtain a second voltage potential difference between the substrate and the first impurity region, the first and third bias voltages being positive and the second bias voltage being negative. The example nonvolatile memory device may include a gate electrode receiving a first bias voltage, a substrate receiving a second bias voltage, the first and second bias voltages forming a first voltage potential difference between the gate electrode and the substrate and a first impurity region receiving a third bias voltage, the second and third bias voltages forming a second voltage potential difference between the first impurity region and the substrate, the first and third bias voltages being positive and the second bias voltage being negative.

Abstract translation: 提供了一种非易失性存储器件及其方法。 示例性方法可以包括向栅电极施加第一偏置电压，向衬底施加第二偏置电压以获得栅电极和衬底之间的第一电压电位差，并向第一杂质区域施加第三偏置电压以获得 所述基板和所述第一杂质区域之间的第二电压电位差，所述第一和第三偏置电压为正，所述第二偏置电压为负。 示例性非易失性存储器件可以包括接收第一偏置电压的栅电极，接收第二偏置电压的衬底，在栅电极和衬底之间形成第一电压电位差的第一和第二偏置电压以及接收第 所述第二偏置电压和所述第三偏置电压在所述第一杂质区域和所述衬底之间形成第二电压电位差，所述第一和第三偏置电压为正，所述第二偏置电压为负。

公开(公告)号：US20070099378A1

公开(公告)日：2007-05-03

申请号：US11535934

申请日：2006-09-27

Applicant: Sang-Su KIM ,  In-Wook Cho ,  Myeong-Cheol Kim ,  Sung-Woo Lee ,  Jin-Hee Kim ,  Doo-Youl Lee ,  Sung-Ho Kim

Inventor： Sang-Su KIM ,  In-Wook Cho ,  Myeong-Cheol Kim ,  Sung-Woo Lee ,  Jin-Hee Kim ,  Doo-Youl Lee ,  Sung-Ho Kim

IPC: H01L21/336 ,  H01L21/00

CPC classification number: H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

Abstract: Disclosed is a semiconductor device having an align key and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having a cell area and an align key area. An isolation layer that defines a cell active area is disposed in the cell area of the semiconductor substrate. A cell charge storage layer pattern is disposed across the cell active area. An align charge storage layer pattern is disposed in the align key area of the semiconductor substrate. An align trench self-aligned with the align charge storage layer pattern is formed in the align key area of the semiconductor substrate.

Abstract translation: 公开了具有对准键的半导体器件及其制造方法。 半导体器件包括具有单元区域和对准键区域的半导体衬底。 限定电池有源区的隔离层设置在半导体衬底的单元区域中。 电池电荷存储层图案跨越电池有源区域设置。 对准电荷存储层图案设置在半导体衬底的对准键区域中。 在对准电荷存储层图案中自对准的对准沟槽形成在半导体衬底的对准键区域中。

公开(公告)号：US07184316B2

公开(公告)日：2007-02-27

申请号：US11038726

申请日：2005-01-19

Applicant: In-Wook Cho ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Byoung-Jin Lee ,  Jin-Hee Kim ,  Byou-Ree Lim ,  Sang-Su Kim

Inventor： In-Wook Cho ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Byoung-Jin Lee ,  Jin-Hee Kim ,  Byou-Ree Lim ,  Sang-Su Kim

IPC: G11C16/04

CPC classification number: G11C16/0425 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

Abstract: A nonvolatile memory cell array having common drain lines and method of operating the same are disclosed. A positive voltage is applied to a gate of a selected cell and gates of memory cells that share a word line with the selected cell. A first voltage is applied to a drain of the selected cell and drains of the memory cells that share at least a drain line with the selected cell. A second voltage is applied to a source of the selected cell and sources of memory cells that share a bit line with the selected cell, the second voltage being less than the first voltage, such that electrons are injected into the charge storage region of the selected cell to program. A third voltage, which is higher than the second voltage, is applied to bit lines that are not connected to the selected cell.

Abstract translation: 公开了一种具有共同漏极线的非易失性存储单元阵列及其操作方法。 将正电压施加到所选单元的栅极和与所选单元共享字线的存储单元的栅极。 将第一电压施加到所选择的单元的漏极和与所选择的单元共享至少漏极线的存储器单元的漏极。 将第二电压施加到所选择的单元的源和与所选择的单元共享位线的存储器单元的源，第二电压小于第一电压，使得电子被注入到所选择的单元的电荷存储区域中 单元格程序。 高于第二电压的第三电压被施加到未连接到所选择的单元的位线。

公开(公告)号：US20060035432A1

公开(公告)日：2006-02-16

申请号：US11146501

申请日：2005-06-07

Applicant: Sang-Su Kim ,  Geum-Jong Bae ,  In-Wook Cho ,  Jin-Hee Kim

Inventor： Sang-Su Kim ,  Geum-Jong Bae ,  In-Wook Cho ,  Jin-Hee Kim

IPC: H01L21/8238

CPC classification number: H01L27/11568 ,  H01L27/105 ,  H01L27/11573 ,  Y10S438/954

Abstract: in methods of fabricating a non-volatile memory device having a local silicon-oxide-nitride-oxide-silicon (SONOS) gate structure, a semiconductor substrate having a cell transistor area, a high voltage transistor area, and a low voltage transistor area, is prepared. At least one memory storage pattern defining a cell gate insulating area on the semiconductor substrate within the cell transistor area is formed. An oxidation barrier layer is formed on the semiconductor substrate within the cell gate insulating area. A lower gate insulating layer is formed on the semiconductor substrate within the high voltage transistor area. A conformal upper insulating layer is formed on the memory storage pattern, the oxidation barrier layer, and the lower gate insulating layer. A low voltage gate insulating layer having a thickness which is less than a combined thickness of the upper insulating layer and the lower gate insulating layer is formed on the semiconductor substrate within the low voltage transistor area.

Abstract translation: 在制造具有局部氧化硅 - 氮化物 - 氧化物 - 硅（SONOS）栅极结构的非易失性存储器件的方法中，具有单元晶体管区域，高压晶体管区域和低压晶体管区域的半导体衬底， 准备好了 形成在单元晶体管区域内的半导体衬底上限定单元栅极绝缘区域的至少一个存储器存储图案。 在单元栅极绝缘区域内的半导体衬底上形成氧化阻挡层。 在高电压晶体管区域内的半导体衬底上形成下栅极绝缘层。 在存储器存储图案，氧化阻挡层和下栅极绝缘层上形成保形的上绝缘层。 在低压晶体管区域内的半导体衬底上形成厚度小于上绝缘层和下栅极绝缘层的组合厚度的低压栅极绝缘层。

公开(公告)号：US20060033152A1

公开(公告)日：2006-02-16

申请号：US11183614

申请日：2005-07-18

Applicant: Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Jin-hee Kim ,  Sang-su Kim

Inventor： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Jin-hee Kim ,  Sang-su Kim

IPC: H01L29/788

CPC classification number: H01L29/66833 ,  H01L21/28282 ,  H01L29/792

Abstract: A non-volatile memory device having improved electrical characteristics and a method of fabricating the non-volatile memory device are provided. The non-volatile memory device includes a gate electrode, which is formed on a semiconductor substrate on which source and drain regions are formed, a trapping structure, which is interposed between the semiconductor substrate and the gate electrode and comprises an electron tunneling layer and a charge trapping layer, and an electron back-tunneling prevention layer, which is interposed between the gate electrode and the charge trapping layer, prevents electrons in the gate electrode from back-tunneling through the charge trapping layer, and is formed of a metal having a higher work function than the gate electrode.

公开(公告)号：US06998309B2

公开(公告)日：2006-02-14

申请号：US10786239

申请日：2004-02-24

Applicant: In-Wook Cho ,  Nae-In Lee ,  Kwang-Wook Koh ,  Geum-Jong Bae ,  Sang-Su Kim ,  Jin-Hee Kim ,  Sung-Ho Kim ,  Ki-Chul Kim

Inventor： In-Wook Cho ,  Nae-In Lee ,  Kwang-Wook Koh ,  Geum-Jong Bae ,  Sang-Su Kim ,  Jin-Hee Kim ,  Sung-Ho Kim ,  Ki-Chul Kim

IPC: H01L21/336

CPC classification number: H01L27/115 ,  H01L27/11568 ,  Y10S438/954

Abstract: A method of manufacturing a non-volatile semiconductor memory device begins by forming a dielectric layer pattern having an ONO composition on a substrate. A polysilicon layer is formed on the substrate including over the dielectric layer pattern. The polysilicon layer is patterned to form a split polysilicon layer pattern that exposes part of the dielectric layer pattern. The exposed dielectric layer is etched, and then impurities are implanted into portions of the substrate using the split polysilicon layer pattern as a mask to thereby form a source region having a vertical profile in the substrate.

Abstract translation: 制造非易失性半导体存储器件的方法是通过在衬底上形成具有ONO组成的电介质层图案而开始的。 在包括在电介质层图案上的衬底上形成多晶硅层。 图案化多晶硅层以形成暴露部分介电层图案的分裂多晶硅层图案。 暴露的电介质层被蚀刻，然后使用分离多晶硅层图案作为掩模将杂质注入到衬底的部分中，从而在衬底中形成具有垂直轮廓的源区。

公开(公告)号：US20050162925A1

公开(公告)日：2005-07-28

申请号：US11038726

申请日：2005-01-19

Applicant: In-Wook Cho ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Byoung-Jin Lee ,  Jin-Hee Kim ,  Byou-Ree Lim ,  Sang-Su Kim

Inventor： In-Wook Cho ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Byoung-Jin Lee ,  Jin-Hee Kim ,  Byou-Ree Lim ,  Sang-Su Kim

IPC: G11C16/02 ,  G11C11/34 ,  G11C16/04 ,  G11C16/06 ,  G11C16/12 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C16/0425 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

Abstract: A nonvolatile memory cell array having common drain lines and method of operating the same are disclosed. A positive voltage is applied to a gate of a selected cell and gates of memory cells that share a word line with the selected cell. A first voltage is applied to a drain of the selected cell and drains of the memory cells that share at least a drain line with the selected cell. A second voltage is applied to a source of the selected cell and sources of memory cells that share a bit line with the selected cell, the second voltage being less than the first voltage, such that electrons are injected into the charge storage region of the selected cell to program. A third voltage, which is higher than the second voltage, is applied to bit lines that are not connected to the selected cell.

Abstract translation: 公开了一种具有共同漏极线的非易失性存储单元阵列及其操作方法。 将正电压施加到所选单元的栅极和与所选单元共享字线的存储单元的栅极。 将第一电压施加到所选择的单元的漏极和与所选择的单元共享至少漏极线的存储器单元的漏极。 第二电压被施加到所选择的单元的源和与所选择的单元共享位线的存储器单元的源，第二电压小于第一电压，使得电子被注入到所选择的单元的电荷存储区域中 单元格程序。 高于第二电压的第三电压被施加到未连接到所选择的单元的位线。

公开(公告)号：US20050067651A1

公开(公告)日：2005-03-31

申请号：US10944382

申请日：2004-09-16

Applicant: Ki-Chul Kim ,  Byou-Ree Lim ,  Sang-Su Kim ,  Byoung-Jin Lee ,  In-Wook Cho

Inventor： Ki-Chul Kim ,  Byou-Ree Lim ,  Sang-Su Kim ,  Byoung-Jin Lee ,  In-Wook Cho

IPC: H01L27/115 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/51 ,  H01L29/792 ,  H01L29/76

CPC classification number: H01L29/792 ,  B82Y10/00 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42332 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833

Abstract: A nonvolatile memory cell employing a plurality of dielectric nanoclusters and a method of fabricating the same are disclosed. In one embodiment, the nonvolatile memory cell comprises a semiconductor substrate having a channel region. A control gate is disposed above the channel region. A control gate dielectric layer is disposed between the channel region and the control gate. A plurality of dielectric nanoclusters are disposed between the channel region and the control gate dielectric layer. Each nanocluster may be separated from adjacent nanoclusters by the control gate dielectric layer. A tunnel oxide layer is disposed between the plurality of dielectric nanoclusters and the channel region. Further, a source and a drain are formed in the semiconductor substrate.

Abstract translation: 公开了一种采用多个电介质纳米簇的非易失性存储单元及其制造方法。 在一个实施例中，非易失性存储单元包括具有沟道区的半导体衬底。 控制门设置在通道区域的上方。 控制栅介质层设置在沟道区和控制栅之间。 多个介电纳米团簇设置在沟道区和控制栅介质层之间。 每个纳米团簇可以通过控制栅极介电层与相邻的纳米团簇分离。 隧道氧化层设置在多个介电纳米簇与沟道区之间。 此外，在半导体衬底中形成源极和漏极。

公开(公告)号：US20050023604A1

公开(公告)日：2005-02-03

申请号：US10844783

申请日：2004-05-13

Applicant: Sang-Su Kim ,  Kwang-Wook Koh ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Sung-Ho Kim ,  Jin-Hee Kim ,  In-Wook Cho

Inventor： Sang-Su Kim ,  Kwang-Wook Koh ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Sung-Ho Kim ,  Jin-Hee Kim ,  In-Wook Cho

IPC: H01L21/8234 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/76 ,  H01L29/788

CPC classification number: H01L27/11568 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

Abstract: The present invention discloses a semiconductor device having a floating trap type nonvolatile memory cell and a method for manufacturing the same. The method includes providing a semiconductor substrate having a nonvolatile memory region, a first region, and a second region. A triple layer composed of a tunnel oxide layer, a charge storing layer and a first deposited oxide layer on the semiconductor substrate is formed sequentially. The triple layer on the semiconductor substrate except the nonvolatile memory region is then removed. A second deposited oxide layer is formed on an entire surface of the semiconductor substrate including the first and second regions from which the triple layer is removed. The second deposited oxide layer on the second region is removed, and a first thermal oxide layer is formed on the entire surface of the semiconductor substrate including the second region from which the second deposited oxide layer is removed. The semiconductor device can be manufactured according to the present invention to have a reduced processing time and a reduced change of impurity doping profile. The thickness of a blocking oxide layer and a high voltage gate oxide layer can be controlled.

Abstract translation: 本发明公开了一种具有浮动阱式非易失性存储单元的半导体器件及其制造方法。 该方法包括提供具有非易失性存储区域，第一区域和第二区域的半导体衬底。 顺序地形成由半导体衬底上的隧道氧化物层，电荷存储层和第一沉积氧化物层组成的三层。 然后除去非易失性存储区域之外的半导体衬底上的三层。 第二沉积氧化物层形成在半导体衬底的包括去除三层的第一和第二区域的整个表面上。 去除第二区域上的第二沉积氧化物层，并且在包括除去第二沉积氧化物层的第二区域的半导体衬底的整个表面上形成第一热氧化物层。 可以根据本发明制造半导体器件以减少处理时间和降低杂质掺杂分布的变化。 可以控制阻挡氧化物层和高电压栅极氧化物层的厚度。