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    Three dimensional strained quantum wells and three dimensional strained surface channels by Ge confinement method
    33.
    发明授权
    Three dimensional strained quantum wells and three dimensional strained surface channels by Ge confinement method 有权
    三维应变量子阱和三维应变表面通道的Ge约束法

    公开(公告)号：US07767560B2

    公开(公告)日：2010-08-03

    申请号：US11864963

    申请日：2007-09-29

    Applicant: Been-Yih Jin ,  Robert S. Chau ,  Brian S. Doyle ,  Jack T. Kavalieros

    Inventor： Been-Yih Jin ,  Robert S. Chau ,  Brian S. Doyle ,  Jack T. Kavalieros

    IPC: H01L21/36 ,  H01L21/20

    CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02664 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/66818 ,  H01L29/7851

    Abstract: The present disclosure describes a method and apparatus for implementing a 3D (three dimensional) strained high mobility quantum well structure, and a 3D strained surface channel structure through a Ge confinement method. One exemplary apparatus may include a first graded SiGe fin on a Si substrate. The first graded SiGe fin may have a maximum Ge concentration greater than about 60%. A Ge quantum well may be on the first graded SiGe fin and a SiGe quantum well upper barrier layer may be on the Ge quantum well. The exemplary apparatus may further include a second graded SiGe fin on the Si substrate. The second graded SiGe fin may have a maximum Ge concentration less than about 40%. A Si active channel layer may be on the second graded SiGe fin. Other high mobility materials such as III-V semiconductors may be used as the active channel materials. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

    Abstract translation: 本公开描述了通过Ge约束法实现3D（三维）应变高迁移量子阱结构和3D应变表面通道结构的方法和装置。 一个示例性设备可以包括在Si衬底上的第一梯度SiGe鳍。 第一级的SiGe鳍可以具有大于约60％的最大Ge浓度。 Ge量子阱可以在第一等级的SiGe鳍上，SiGe量子阱上阻挡层可以在Ge量子阱上。 示例性设备还可以包括在Si衬底上的第二渐变SiGe鳍。 第二级的SiGe鳍可以具有小于约40％的最大Ge浓度。 Si活性沟道层可以在第二级别的SiGe鳍上。 可以使用诸如III-V族半导体的其它高迁移率材料作为活性通道材料。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

    Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin
    34.
    发明授权
    Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin 有权
    通过结合部分金属翅片来减少多栅极器件的外部电阻

    公开(公告)号：US07763943B2

    公开(公告)日：2010-07-27

    申请号：US11964623

    申请日：2007-12-26

    Applicant: Ravi Pillarisetty ,  Uday Shah ,  Titash Rakshit ,  Jack T. Kavalieros ,  Brian S. Doyle

    Inventor： Ravi Pillarisetty ,  Uday Shah ,  Titash Rakshit ,  Jack T. Kavalieros ,  Brian S. Doyle

    IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062

    CPC classification number: H01L29/785 ,  H01L29/66795

    Abstract: Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin is generally described. In one example, an apparatus includes a semiconductor substrate and one or more fins of a multi-gate transistor device coupled with the semiconductor substrate, the one or more fins having a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions where the gate region of the one or more fins includes a semiconductor material and where the source and drain regions of the one or more fins include a metal portion and a semiconductor portion, the metal portion and the semiconductor portion being coupled together.

    Abstract translation: 通常描述通过结合部分金属翅片来降低多栅极器件的外部电阻。 在一个示例中，设备包括半导体衬底和与半导体衬底耦合的多栅极晶体管器件的一个或多个鳍片，该一个或多个鳍片具有栅极区域，源极区域和漏极区域，栅极区域 设置在源极和漏极区域之间，其中一个或多个鳍片的栅极区域包括半导体材料，并且其中一个或多个鳍片的源极和漏极区域包括金属部分和半导体部分，金属部分和半导体 部分联接在一起。

    Tri-gate patterning using dual layer gate stack
    36.
    发明授权
    Tri-gate patterning using dual layer gate stack 有权
    使用双层栅极堆叠的三栅极图案化

    公开(公告)号：US07745270B2

    公开(公告)日：2010-06-29

    申请号：US12006047

    申请日：2007-12-28

    Applicant: Uday Shah ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Been-Yih Jin

    Inventor： Uday Shah ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Been-Yih Jin

    IPC: H01L21/84

    CPC classification number: H01L21/823821 ,  H01L29/66795 ,  H01L29/785

    Abstract: In general, in one aspect, a method includes forming an n-diffusion fin and a p-diffusion fin in a semiconductor substrate. A high dielectric constant layer is formed over the substrate. A first work function metal layer is created over the n-diffusion fin and a second work function metal layer, thicker than the first, is created over the n-diffusion fin. A silicon germanium layer is formed over the first and second work function metal layers. A polysilicon layer is formed over the silicon germanium layer and is polished. The polysilicon layer over the first work function metal layer is thicker than the polysilicon layer over the second work function metal layer. A hard mask is patterned and used to etch the polysilicon layer and the silicon germanium layer to create gate stacks. The etch rate of the silicon germanium layer is faster over the first work function metal layer.

    Abstract translation: 通常，在一个方面，一种方法包括在半导体衬底中形成n扩散鳍和p扩散鳍。 在衬底上形成高介电常数层。 在n扩散翅片上形成第一功函数金属层，并在n扩散鳍片上形成比第一功函数金属层厚的第二功函数金属层。 在第一和第二功函数金属层上形成硅锗层。 在硅锗层上形成多晶硅层并进行抛光。 第一功函数金属层上的多晶硅层比第二功函数金属层上的多晶硅层厚。 硬掩模被图案化并用于蚀刻多晶硅层和硅锗层以产生栅极堆叠。 硅锗层的蚀刻速率比第一功函数金属层更快。

    Fabrication of germanium nanowire transistors
    37.
    发明授权
    Fabrication of germanium nanowire transistors 有权
    锗纳米线晶体管的制造

    公开(公告)号：US07727830B2

    公开(公告)日：2010-06-01

    申请号：US12006273

    申请日：2007-12-31

    Applicant: Been-Yih Jin ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Marko Radosavlievic ,  Robert S. Chau

    Inventor： Been-Yih Jin ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Marko Radosavlievic ,  Robert S. Chau

    IPC: H01L21/337

    CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/78684 ,  H01L29/78696

    Abstract: In general, in one aspect, a method includes using the Germanium nanowire as building block for high performance logic, memory and low dimensional quantum effect devices. The Germanium nanowire channel and the SiGe anchoring regions are formed simultaneously through preferential Si oxidation of epitaxial Silicon Germanium epi layer. The placement of the germanium nanowires is accomplished using a Si fin as a template and the germanium nanowire is held on Si substrate through SiGe anchors created by masking the two ends of the fins. High dielectric constant gate oxide and work function metals wrap around the Germanium nanowire for gate-all-around electrostatic channel on/off control, while the Germanium nanowire provides high carrier mobility in the transistor channel region. The germanium nanowire transistors enable high performance, low voltage (low power consumption) operation of logic and memory devices.

    Abstract translation: 通常，在一个方面，一种方法包括使用锗纳米线作为高性能逻辑，存储器和低维量子效应器件的构建块。 锗纳米线通道和SiGe锚定区域通过外延硅锗外延层的优先Si氧化同时形成。 使用Si翅片作为模板来实现锗纳米线的放置，并且锗纳米线通过掩蔽翅片的两端而形成的SiGe锚定件保持在Si衬底上。 高介电常数栅极氧化物和功函数金属缠绕在锗纳米线上，用于门极全静电通道开/关控制，而锗纳米线在晶体管沟道区域提供高载流子迁移率。 锗纳米线晶体管可实现逻辑和存储器件的高性能，低电压（低功耗）操作。

    Defect-free source/drain extensions for MOSFETS having germanium based channel regions
    40.
    发明授权
    Defect-free source/drain extensions for MOSFETS having germanium based channel regions 有权
    具有锗基通道区域的MOSFET的无缺陷源极/漏极扩展

    公开(公告)号：US07545003B2

    公开(公告)日：2009-06-09

    申请号：US11864907

    申请日：2007-09-29

    Applicant: Prashant Majhi ,  William Tsai ,  Jack T. Kavalieros

    Inventor： Prashant Majhi ,  William Tsai ,  Jack T. Kavalieros

    IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC classification number: H01L29/6659 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/7833

    Abstract: A process for forming defect-free source and drain extensions for a MOSFET built on a germanium based channel region deposits a first silicon germanium layer on a semiconductor substrate, deposits a gate dielectric layer on the silicon germanium layer, and deposits a gate electrode layer on the gate dielectric layer. A dry etch chemistry etches those layers to form a gate electrode, a gate dielectric, and a silicon germanium channel region on the semiconductor substrate. Next, an ion implantation process forms halo implant regions that consume portions of the silicon germanium channel region and the semiconductor substrate. Finally, an in-situ doped epitaxial deposition process grows a pair of silicon germanium layers having LDD regions. The silicon germanium layers are adjacent to the silicon germanium channel region and the halo implant regions do not damage any portion of the silicon germanium layers.

    Abstract translation: 用于形成用于基于锗基通道区域的MOSFET的无缺陷源极和漏极延伸的工艺在半导体衬底上沉积第一硅锗层，在硅锗层上沉积栅极电介质层，并将栅极电极层沉积在 栅介质层。 干蚀刻化学蚀刻这些层以在半导体衬底上形成栅电极，栅极电介质和硅锗沟道区。 接下来，离子注入工艺形成消耗硅锗沟道区和半导体衬底的部分的卤素注入区。 最后，原位掺杂外延沉积工艺生长了一对具有LDD区的硅锗层。 硅锗层与硅锗沟道区相邻，并且卤素注入区不会损坏硅锗层的任何部分。

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