公开(公告)号：US08081537B1

公开(公告)日：2011-12-20

申请号：US13154172

申请日：2011-06-06

Applicant: Jayesh R. Bhakta ,  Jeffrey C. Solomon

Inventor： Jayesh R. Bhakta ,  Jeffrey C. Solomon

IPC: G11C8/00

CPC classification number: G11C8/12 ,  G06F12/0207 ,  G06F12/0215 ,  G11C5/04 ,  G11C5/066 ,  G11C7/1048 ,  G11C2207/105 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2203/1572 ,  Y02P70/611

Abstract: A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The memory module has a first number of ranks of double-data-rate (DDR) memory devices activated at least in part to a first number of chip-select signals. The circuit is configurable to receive address signals and a second number of chip-select signals from the computer system. The circuit is further configurable to generate and transmit phase-locked clock signals to the first number of ranks, and to generate the first number of chip-select signals in response at least in part to the phase-locked clock signals, the address signals, and the second number of chip-select signals.

Abstract translation: 电路被配置为安装在可连接到计算机系统的存储器模块上，以便电耦合到存储器模块上的多个存储器件。 存储器模块具有至少部分地针对第一数量的芯片选择信号而激活的第一数量的双数据速率（DDR）存储器设备。 电路可配置为从计算机系统接收地址信号和第二数量的芯片选择信号。 该电路还可配置为产生并将锁相时钟信号发送到第一数量的等级，并且至少部分地响应于锁相时钟信号，地址信号， 和第二数量的芯片选择信号。

公开(公告)号：US08072837B1

公开(公告)日：2011-12-06

申请号：US12981380

申请日：2010-12-29

Applicant: Jeffrey C. Solomon ,  Jayesh R. Bhakta

Inventor： Jeffrey C. Solomon ,  Jayesh R. Bhakta

IPC: G11C8/00

CPC classification number: G06F13/1673 ,  G06F12/00 ,  G06F13/00 ,  G06F13/4243 ,  G06F13/4282 ,  G11C5/04 ,  G11C7/1072 ,  G11C15/00

Abstract: A circuit is configured to be mounted on a memory module configured to be operationally coupled to a computer system. The memory module has a first number of ranks of double-data-rate (DDR) memory devices configured to be activated concurrently with one another in response to a first number of chip-select signals. The circuit is configurable to receive a set of signals comprising address signals and a second number of chip-select signals, the address signals comprising bank address signals. The circuit is further configurable to monitor command signals received by the memory module, to selectively isolate a load of at least one rank of the first number of ranks from the computer system in response to the command signals, and to provide the first number of chip-select signals to the first number of ranks in response at least in part to the received bank address signals and the received second number of chip-select signals.

Abstract translation: 电路被配置为安装在被配置为可操作地耦合到计算机系统的存储器模块上。 存储器模块具有被配置为响应于第一数量的芯片选择信号彼此同时激活的第二数量的双数据速率（DDR）存储器设备。 电路可配置为接收包括地址信号和第二数量的芯片选择信号的一组信号，地址信号包括存储体地址信号。 该电路还可配置为监视由存储器模块接收的命令信号，以响应于命令信号选择性地隔离来自计算机系统的第一数量级的至少一级的负载，并提供第一数量的芯片 - 至少部分地响应于所接收的存储体地址信号和所接收的第二数量的芯片选择信号，选择到第一数量级的信号。

公开(公告)号：US20110085406A1

公开(公告)日：2011-04-14

申请号：US12955711

申请日：2010-11-29

Applicant: Jeffrey C. Solomon ,  Jayesh R. Bhakta

Inventor： Jeffrey C. Solomon ,  Jayesh R. Bhakta

IPC: G11C8/16 ,  G11C8/06 ,  G11C8/18

CPC classification number: G06F13/1673 ,  G06F12/00 ,  G06F13/00 ,  G06F13/4243 ,  G06F13/4282 ,  G11C5/04 ,  G11C7/1072 ,  G11C15/00

Abstract: A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The memory module has a first number of ranks of double-data-rate (DDR) memory devices activated by a first number of chip-select signals. The circuit is configurable to receive bank address signals, a second number of chip-select signals, and row/column address signals from the computer system. The circuit is further configurable to generate phase-locked clock signals in response to clock signals received from the computer system, to selectively isolate one or more loads of the first number of ranks from the computer system, and to translate between a system memory domain and a physical memory domain of the memory module.

Abstract translation: 电路被配置为安装在可连接到计算机系统的存储器模块上，以便电耦合到存储器模块上的多个存储器件。 存储器模块具有由第一数量的芯片选择信号激活的第二数量的双数据速率（DDR）存储器件。 电路可配置为接收来自计算机系统的存储体地址信号，第二数量的芯片选择信号和行/列地址信号。 该电路还可配置为响应于从计算机系统接收的时钟信号而产生锁相时钟信号，以便选择性地将计算机系统中的第一数量级别的一个或多个负载隔离，并在系统存储器域和 存储器模块的物理内存域。

公开(公告)号：US07881150B2

公开(公告)日：2011-02-01

申请号：US12629827

申请日：2009-12-02

Applicant: Jeffrey C. Solomon ,  Jayesh R. Bhakta

Inventor： Jeffrey C. Solomon ,  Jayesh R. Bhakta

IPC: G11C8/16

CPC classification number: G11C5/04 ,  G06F12/0207 ,  G06F12/0215 ,  G11C5/066 ,  G11C7/1048 ,  G11C8/12 ,  G11C2207/105 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2203/1572 ,  Y02D10/13 ,  Y02P70/611

Abstract: A circuit is configured to be mounted on a memory module so as to be electrically coupled to a plurality of double-data-rate (DDR) memory devices arranged in one or more ranks on the memory module. The circuit includes a logic element, a register, and a phase-lock loop device. The circuit is configurable to respond to a set of input signals from a computer system to selectively isolate one or more loads of the plurality of DDR memory devices from the computer system and to translate between a system memory domain of the computer system and a physical memory domain of the plurality of DDR memory devices.

Abstract translation: 电路被配置为安装在存储器模块上，以便电耦合到在存储器模块上以一个或多个等级布置的多个双数据速率（DDR）存储器件。 该电路包括逻辑元件，寄存器和锁相环装置。 电路可配置为响应来自计算机系统的一组输入信号，以选择性地将多个DDR存储器设备的一个或多个负载与计算机系统隔离开来，并在计算机系统的系统存储器域与物理存储器 域的多个DDR存储器件。

公开(公告)号：US20100128507A1

公开(公告)日：2010-05-27

申请号：US12629827

申请日：2009-12-02

Applicant: Jeffrey C. Solomon ,  Jayesh R. Bhakta

Inventor： Jeffrey C. Solomon ,  Jayesh R. Bhakta

IPC: G11C5/02 ,  G11C7/00 ,  G11C8/16

CPC classification number: G11C5/04 ,  G06F12/0207 ,  G06F12/0215 ,  G11C5/066 ,  G11C7/1048 ,  G11C8/12 ,  G11C2207/105 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2203/1572 ,  Y02D10/13 ,  Y02P70/611

Abstract: A circuit is configured to be mounted on a memory module so as to be electrically coupled to a plurality of double-data-rate (DDR) memory devices arranged in one or more ranks on the memory module. The circuit includes a logic element, a register, and a phase-lock loop device. The circuit is configurable to respond to a set of input signals from a computer system to selectively isolate one or more loads of the plurality of DDR memory devices from the computer system and to translate between a system memory domain of the computer system and a physical memory domain of the plurality of DDR memory devices.

Abstract translation: 电路被配置为安装在存储器模块上，以便电耦合到在存储器模块上以一个或多个等级布置的多个双数据速率（DDR）存储器件。 该电路包括逻辑元件，寄存器和锁相环装置。 电路可配置为响应来自计算机系统的一组输入信号，以选择性地将多个DDR存储器设备的一个或多个负载与计算机系统隔离开来，并在计算机系统的系统存储器域与物理存储器 域的多个DDR存储器件。

公开(公告)号：US07636274B2

公开(公告)日：2009-12-22

申请号：US12408652

申请日：2009-03-20

Applicant: Jeffrey C Solomon ,  Jayesh R Bhakta

Inventor： Jeffrey C Solomon ,  Jayesh R Bhakta

IPC: G11C8/16

CPC classification number: G11C5/04 ,  G06F12/0207 ,  G06F12/0215 ,  G11C5/066 ,  G11C7/1048 ,  G11C8/12 ,  G11C2207/105 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2203/1572 ,  Y02D10/13 ,  Y02P70/611

Abstract: A memory module includes a plurality of memory devices and a circuit. Each memory device has a corresponding load. The circuit is electrically coupled to the plurality of memory devices and is configured to be electrically coupled to a memory controller of a computer system. The circuit selectively isolates one or more of the loads of the memory devices from the computer system. The circuit comprises logic which translates between a system memory domain of the computer system and a physical memory domain of the memory module.

Abstract translation: 存储器模块包括多个存储器件和电路。 每个存储器件具有相应的负载。 电路电耦合到多个存储器件并被配置为电耦合到计算机系统的存储器控​​制器。 该电路选择性地将存储器件的一个或多个负载与计算机系统隔离。 该电路包括在计算机系统的系统存储器域和存储器模块的物理存储器域之间转换的逻辑。

公开(公告)号：US07289386B2

公开(公告)日：2007-10-30

申请号：US11173175

申请日：2005-07-01

Applicant: Jayesh R. Bhakta ,  Jeffrey C. Solomon

Inventor： Jayesh R. Bhakta ,  Jeffrey C. Solomon

IPC: G11C8/00

CPC classification number: G11C8/12 ,  G06F12/0207 ,  G06F12/0215 ,  G11C5/04 ,  G11C5/066 ,  G11C7/1048 ,  G11C2207/105 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2203/1572 ,  Y02P70/611

Abstract: A memory module connectable to a computer system includes a printed circuit board, a plurality of memory devices coupled to the printed circuit board, and a logic element coupled to the printed circuit board. The plurality of memory devices has a first number of memory devices. The logic element receives a set of input control signals from the computer system. The set of input control signals corresponds to a second number of memory devices smaller than the first number of memory devices. The logic element generates a set of output control signals in response to the set of input control signals. The set of output control signals corresponds to the first number of memory devices.

Abstract translation: 可连接到计算机系统的存储器模块包括印刷电路板，耦合到印刷电路板的多个存储器件以及耦合到印刷电路板的逻辑元件。 多个存储器件具有第一数量的存储器件。 逻辑元件从计算机系统接收一组输入控制信号。 该组输入控制信号对应于小于第一数量的存储器件的第二数量的存储器件。 逻辑元件响应于该组输入控制信号产生一组输出控制信号。 该组输出控制信号对应于第一数量的存储器件。

公开(公告)号：US06930900B2

公开(公告)日：2005-08-16

申请号：US10765420

申请日：2004-01-27

Applicant: Jayesh R. Bhakta ,  Robert S. Pauley, Jr.

Inventor： Jayesh R. Bhakta ,  Robert S. Pauley, Jr.

IPC: G11C5/00 ,  H05K1/02 ,  H05K1/18 ,  G11C5/06 ,  G06F12/00 ,  G06F13/00 ,  G11C5/02 ,  G11C19/00

CPC classification number: H05K1/181 ,  H05K1/0266 ,  H05K2201/09409 ,  H05K2201/09709 ,  H05K2201/10689 ,  Y02P70/611

Abstract: Integrated circuits utilizing standard commercial packaging are arranged on a printed circuit board to allow the production of 1-Gigabyte and 2-Gigabyte capacity memory modules. A first row of integrated circuits is oriented in an opposite orientation to a second row of integrated circuits. The integrated circuits in a first half of the first row and in the corresponding half of the second row are connected via a signal trace to a first register. The integrated circuits in a second half of the first row and in the corresponding half of the second row are connected to a second register. Each register processes a non-contiguous subset of the bits in each data word.

公开(公告)号：US06222739B1

公开(公告)日：2001-04-24

申请号：US09228867

申请日：1999-01-12

Applicant: Jayesh R. Bhakta ,  Kavous Vakilian

Inventor： Jayesh R. Bhakta ,  Kavous Vakilian

IPC: H05K111

CPC classification number: G06F1/186 ,  G06F1/184 ,  G06F1/185 ,  H01L25/105 ,  H01L25/16 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/0002 ,  H01R12/721 ,  H05K1/144 ,  H05K7/1431 ,  H01L2924/00

Abstract: A module for insertion into an expansion slot of a computer includes a primary board and a pair of auxiliary boards. The auxiliary boards are mounted in a spaced relationship on respective sides of the primary board to define air paths between the boards. The air paths allow air to circulate between the boards. The auxiliary boards each have a trace for electrically connecting the board to the primary board, and the primary board has a trace for connecting chips mounted thereon to an interface with the expansion slot. The traces of the auxiliary boards are substantially the same length. The trace of the primary boards is only slightly longer than the traces of the auxiliary boards.

Abstract translation: 用于插入到计算机的扩展槽中的模块包括主板和一对辅助板。 辅助板在主板的相应侧面上以间隔的关系安装，以限定板之间的空气路径。 空气路径允许空气在板之间循环。 辅助板各自具有用于将板电连接到主板的迹线，并且主板具有用于将安装在其上的芯片连接到与扩展槽的接口的迹线。 辅助板的迹线基本上相同的长度。 主板的轨迹只比辅助板的轨迹略长。

公开(公告)号：US08782350B2

公开(公告)日：2014-07-15

申请号：US13412243

申请日：2012-03-05

Applicant: Hyun Lee ,  Jayesh R. Bhakta ,  Jeffrey C. Solomon ,  Mario Jesus Martinez ,  Chi-She Chen

Inventor： Hyun Lee ,  Jayesh R. Bhakta ,  Jeffrey C. Solomon ,  Mario Jesus Martinez ,  Chi-She Chen

IPC: G06F12/00 ,  H05K1/02

CPC classification number: G06F13/1684 ,  G06F13/4027 ,  G11C5/02 ,  G11C5/06 ,  G11C8/18 ,  H05K1/0216 ,  H05K1/0243 ,  H05K2201/10053 ,  H05K2201/10159 ,  H05K2201/10189

Abstract: Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a computer system. The memory module further includes a plurality of memory devices on the printed circuit board and a circuit including a first set of ports operatively coupled to at least one memory device. The circuit further includes a second set of ports operatively coupled to the at least one connector. The circuit includes a switching circuit configured to selectively operatively couple one or more ports of the second set of ports to one or more ports of the first set of ports. Each port of the first set and the second set comprises a correction circuit which reduces noise in one or more signals transmitted between the first set of ports and the second set of ports.

Abstract translation: 本文描述的某些实施例包括具有印刷电路板的存储器模块，该印刷电路板包括被配置为可操作地耦合到计算机系统的存储器控​​制器的至少一个连接器。 存储器模块还包括印刷电路板上的多个存储器件和包括可操作地耦合到至少一个存储器件的第一组端口的电路。 电路还包括可操作地耦合到至少一个连接器的第二组端口。 电路包括切换电路，其被配置为选择性地将第二组端口的一个或多个端口耦合到第一组端口的一个或多个端口。 第一组和第二组的每个端口包括校正电路，其减少在第一组端口和第二组端口之间传输的一个或多个信号中的噪声。